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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-10-02 22:08:09 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-10-02 22:08:09 -0700 |
| commit | 7c521db9de281326f35a5743e1b4777a8e2bb2f4 (patch) | |
| tree | 795567aac56636d4e671307295ebafff5aa5c3bd /src/arch/x86/tlb.hh | |
| parent | 683d6d46f6da1e0e0f377a5be1a14f7b6b4233a4 (diff) | |
| download | gem5-7c521db9de281326f35a5743e1b4777a8e2bb2f4.tar.xz | |
X86: Implement the ldst microop and put it in existing microcode where appropriate.
--HG--
extra : convert_revision : f08bd725d07a501bb7a0ce91590b5d37db99c6f3
Diffstat (limited to 'src/arch/x86/tlb.hh')
| -rw-r--r-- | src/arch/x86/tlb.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 386d1635d..24373c623 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -62,6 +62,7 @@ #if FULL_SYSTEM +#include "arch/segmentregs.hh" #include "mem/request.hh" #include "params/X86DTB.hh" #include "params/X86ITB.hh" @@ -73,6 +74,8 @@ class Packet; namespace X86ISA { + static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS; + struct TlbEntry { Addr pageStart; @@ -134,6 +137,7 @@ class DTB : public TLB #include <iostream> +#include "arch/x86/segmentregs.hh" #include "sim/host.hh" #include "sim/tlb.hh" @@ -141,6 +145,8 @@ class Checkpoint; namespace X86ISA { + static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS; + struct TlbEntry { Addr pageStart; |