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author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-18 15:11:44 +0800 |
commit | ce003b28a15104574bed634923564a6bd910898d (patch) | |
tree | d4ac3b5be20f0354e717a4854f981d4a4c21065b /src/arch/x86/tlb.hh | |
parent | 4cc9473c971650153d148b74ad67e50e54828a99 (diff) | |
download | gem5-ce003b28a15104574bed634923564a6bd910898d.tar.xz |
invisispec-1.0 source
Diffstat (limited to 'src/arch/x86/tlb.hh')
-rw-r--r-- | src/arch/x86/tlb.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 08804a455..9e9c8fa05 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -105,6 +105,7 @@ namespace X86ISA Stats::Scalar wrAccesses; Stats::Scalar rdMisses; Stats::Scalar wrMisses; + Stats::Scalar specMisses; Fault translateInt(RequestPtr req, ThreadContext *tc); |