X86: Use the AddrTrie class to implement the TLB.

This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.

1 files changed, 12 insertions, 0 deletions

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index bcadda762..1d1204cfe 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -46,6 +46,7 @@
 
 #include "arch/x86/regs/segment.hh"
 #include "arch/x86/pagetable.hh"
+#include "base/trie.hh"
 #include "mem/mem_object.hh"
 #include "mem/request.hh"
 #include "params/X86TLB.hh"
@@ -103,6 +104,9 @@ namespace X86ISA
         EntryList freeList;
         EntryList entryList;
 
+        TlbEntryTrie trie;
+        uint64_t lruSeq;
+
         Fault translateInt(RequestPtr req, ThreadContext *tc);
 
         Fault translate(RequestPtr req, ThreadContext *tc,
@@ -111,6 +115,14 @@ namespace X86ISA
 
       public:
 
+        void evictLRU();
+
+        uint64_t
+        nextSeq()
+        {
+            return ++lruSeq;
+        }
+
         Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
         void translateTiming(RequestPtr req, ThreadContext *tc,
                 Translation *translation, Mode mode);