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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-20 16:08:09 +0800 |
| commit | 0ca254aa8381ba2fae61a4a056301e35da9ffab3 (patch) | |
| tree | 612664055ade4cca58186a76fee4dd7522aeb305 /src/arch/x86/tlb.hh | |
| parent | 476fd104a80095207eec0b594baa642937fbac01 (diff) | |
| download | gem5-0ca254aa8381ba2fae61a4a056301e35da9ffab3.tar.xz | |
invisispec-1.0 source
Diffstat (limited to 'src/arch/x86/tlb.hh')
| -rw-r--r-- | src/arch/x86/tlb.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 827ab8166..7213b8b41 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -105,6 +105,7 @@ namespace X86ISA Stats::Scalar wrAccesses; Stats::Scalar rdMisses; Stats::Scalar wrMisses; + Stats::Scalar specMisses; Fault translateInt(const RequestPtr &req, ThreadContext *tc); |