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author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
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committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/arch/x86/utility.cc | |
parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/arch/x86/utility.cc')
-rw-r--r-- | src/arch/x86/utility.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc index b50b99dfa..df7d3935d 100644 --- a/src/arch/x86/utility.cc +++ b/src/arch/x86/utility.cc @@ -244,6 +244,8 @@ copyRegs(ThreadContext *src, ThreadContext *dest) //copy float regs for (int i = 0; i < NumFloatRegs; ++i) dest->setFloatRegBits(i, src->readFloatRegBits(i)); + // Will need to add condition-code regs when implemented + assert(NumCCRegs == 0); copyMiscRegs(src, dest); dest->pcState(src->pcState()); } |