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author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-07 10:13:20 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-07 10:13:20 -0700 |
commit | 3a55fc5cace5fdf744a891c6d32c4a9d4c10694a (patch) | |
tree | 36695ff44c29ff0b249d66e4fc05957e903c45ed /src/arch/x86/x86_traits.hh | |
parent | 62a2e85c9a0af39970568b35afa4d050ef571b23 (diff) | |
download | gem5-3a55fc5cace5fdf744a891c6d32c4a9d4c10694a.tar.xz |
X86: Implement shift right/left double microops.
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.
Diffstat (limited to 'src/arch/x86/x86_traits.hh')
-rw-r--r-- | src/arch/x86/x86_traits.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index 8b50bdf9b..a73aaef19 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -68,12 +68,13 @@ namespace X86ISA const int NumPseudoIntRegs = 1; //1. The condition code bits of the rflags register. - const int NumImplicitIntRegs = 5; + const int NumImplicitIntRegs = 6; //1. The lower part of the result of multiplication. //2. The upper part of the result of multiplication. //3. The quotient from division //4. The remainder from division //5. The divisor for division + //6. The register to use for shift doubles const int NumMMXRegs = 8; const int NumXMMRegs = 16; |