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| author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
|---|---|---|
| committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
| commit | 1bb293d1e7a27e306ca584a3922f2fd13481e248 (patch) | |
| tree | 21d457f5c7d7e2e836eaf944b7d82964fc64d1bd /src/arch/x86/x86_traits.hh | |
| parent | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (diff) | |
| download | gem5-1bb293d1e7a27e306ca584a3922f2fd13481e248.tar.xz | |
arch/x86: add support for explicit CC register file
Convert condition code registers from being specialized
("pseudo") integer registers to using the recently
added CC register class.
Nilay Vaish also contributed to this patch.
Diffstat (limited to 'src/arch/x86/x86_traits.hh')
| -rw-r--r-- | src/arch/x86/x86_traits.hh | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index 408fda106..6f1c9ae36 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -46,8 +46,6 @@ namespace X86ISA { const int NumMicroIntRegs = 16; - const int NumPseudoIntRegs = 5; - //1. The condition code bits of the rflags register. const int NumImplicitIntRegs = 6; //1. The lower part of the result of multiplication. //2. The upper part of the result of multiplication. |