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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-10-12 16:37:55 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-10-12 16:37:55 -0700 |
| commit | 9498e536c0231b808669f2bacb4c0628d1ec309a (patch) | |
| tree | 13edd1623e87077269a03b10a37a66bf61f4f969 /src/arch/x86/x86_traits.hh | |
| parent | 8b35bd6fe79ce069428431a4edbe43b8373f7e87 (diff) | |
| download | gem5-9498e536c0231b808669f2bacb4c0628d1ec309a.tar.xz | |
X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.
--HG--
extra : convert_revision : ff893eb569313d8aecbfffb47bcbd1c2d65cd393
Diffstat (limited to 'src/arch/x86/x86_traits.hh')
| -rw-r--r-- | src/arch/x86/x86_traits.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index 33ec13372..beb1898ce 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -55,6 +55,8 @@ * Authors: Gabe Black */ +#include "sim/host.hh" + #ifndef __ARCH_X86_X86TRAITS_HH__ #define __ARCH_X86_X86TRAITS_HH__ @@ -80,6 +82,10 @@ namespace X86ISA const int NumSegments = 6; const int NumSysSegments = 4; + + const Addr IntAddrPrefixMask = ULL(0xffffffff00000000); + const Addr IntAddrPrefixCPUID = ULL(0x100000000); + const Addr IntAddrPrefixMSR = ULL(0x200000000); } #endif //__ARCH_X86_X86TRAITS_HH__ |