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authorVince Weaver <vince@csl.cornell.edu>2009-10-21 13:40:43 -0400
committerVince Weaver <vince@csl.cornell.edu>2009-10-21 13:40:43 -0400
commit14691148cd9300ed7a23dd889b9c0173124b30eb (patch)
tree4c73311d2302e94b9aed67ae70d36e184614b45b /src/arch/x86
parent5b6f707a008b4312fd02a4383bf107adfa677d33 (diff)
downloadgem5-14691148cd9300ed7a23dd889b9c0173124b30eb.tar.xz
Implement X86 sse2 movdqu and movdqa instructions
The movdqa instruction should enforce 16-byte alignment. This implementation does not do that. These instructions are needed for most of x86_64 spec2k to run.
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa8
-rw-r--r--src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py56
2 files changed, 58 insertions, 6 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index c23eeccab..27aabaccc 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -604,7 +604,7 @@
}
// repe (0xF3)
0x4: decode OPCODE_OP_BOTTOM3 {
- 0x7: WarnUnimpl::movdqu_Vo_Wo();
+ 0x7: MOVDQU(Vo,Wo);
default: UD2();
}
// operand size (0x66)
@@ -616,7 +616,7 @@
0x4: PUNPCKLQDQ(Vo,Wq);
0x5: PUNPCKHQDQ(Vo,Wq);
0x6: WarnUnimpl::movd_Vo_Ed();
- 0x7: WarnUnimpl::movdqa_Vo_Wo();
+ 0x7: MOVDQA(Vo,Wo);
}
default: UD2();
}
@@ -702,7 +702,7 @@
// repe (0xF3)
0x4: decode OPCODE_OP_BOTTOM3 {
0x6: MOVQ(Vq,Wq);
- 0x7: WarnUnimpl::movdqu_Wo_Vo();
+ 0x7: MOVDQU(Wo,Vo);
default: UD2();
}
// operand size (0x66)
@@ -710,7 +710,7 @@
0x4: WarnUnimpl::haddpd_Vo_Wo();
0x5: WarnUnimpl::hsubpd_Vo_Wo();
0x6: WarnUnimpl::movd_Ed_Vd();
- 0x7: WarnUnimpl::movdqa_Wo_Vo();
+ 0x7: MOVDQA(Wo,Vo);
default: UD2();
}
// repne (0xF2)
diff --git a/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py
index c34bd42bb..ec80ffe73 100644
--- a/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py
@@ -87,7 +87,59 @@ def macroop MOVQ2DQ_XMM_MMX {
movfp xmml, mmxm, dataSize=8
lfpimm xmmh, 0
};
+
+def macroop MOVDQA_XMM_XMM {
+ movfp xmml, xmmlm
+ movfp xmmh, xmmhm
+};
+
+def macroop MOVDQA_XMM_M {
+ ldfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
+ ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQA_XMM_P {
+ rdip t7
+ ldfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
+ ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQA_M_XMM {
+ stfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
+ stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQA_P_XMM {
+ rdip t7
+ stfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
+ stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQU_XMM_XMM {
+ movfp xmml, xmmlm
+ movfp xmmh, xmmhm
+};
+
+def macroop MOVDQU_XMM_M {
+ ldfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
+ ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQU_XMM_P {
+ rdip t7
+ ldfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
+ ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQU_M_XMM {
+ stfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
+ stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQU_P_XMM {
+ rdip t7
+ stfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
+ stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+};
'''
-# MOVDQA
-# MOVDQU
# LDDQU