ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.

This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.

17 files changed, 105 insertions, 52 deletions

diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 4f2d97f90..7fb677c69 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -58,7 +58,8 @@ namespace X86ISA
 #if FULL_SYSTEM
     void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
-        Addr pc = tc->readPC();
+        PCState pcState = tc->pcState();
+        Addr pc = pcState.pc();
         DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
         using namespace X86ISAInst::RomLabels;
         HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
@@ -86,8 +87,9 @@ namespace X86ISA
             assert(!isSoft());
             tc->setIntReg(INTREG_MICRO(15), errorCode);
         }
-        tc->setMicroPC(romMicroPC(entry));
-        tc->setNextMicroPC(romMicroPC(entry) + 1);
+        pcState.upc(romMicroPC(entry));
+        pcState.nupc(romMicroPC(entry) + 1);
+        tc->pcState(pcState);
     }
 
     std::string
@@ -106,9 +108,8 @@ namespace X86ISA
     {
         X86FaultBase::invoke(tc);
         // This is the same as a fault, but it happens -after- the instruction.
-        tc->setPC(tc->readNextPC());
-        tc->setNextPC(tc->readNextNPC());
-        tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
+        PCState pc = tc->pcState();
+        pc.uEnd();
     }
 
     void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
@@ -207,9 +208,8 @@ namespace X86ISA
         tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
         tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
 
-        tc->setPC(0x000000000000fff0ULL +
-                tc->readMiscReg(MISCREG_CS_BASE));
-        tc->setNextPC(tc->readPC() + sizeof(MachInst));
+        PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
+        tc->pcState(pc);
 
         tc->setMiscReg(MISCREG_TSG_BASE, 0);
         tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
@@ -243,8 +243,9 @@ namespace X86ISA
         // Update the handy M5 Reg.
         tc->setMiscReg(MISCREG_M5_REG, 0);
         MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
-        tc->setMicroPC(romMicroPC(entry));
-        tc->setNextMicroPC(romMicroPC(entry) + 1);
+        pc.upc(romMicroPC(entry));
+        pc.nupc(romMicroPC(entry) + 1);
+        tc->pcState(pc);
     }
 
     void
@@ -263,8 +264,7 @@ namespace X86ISA
         // This has the base value pre-added.
         tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
 
-        tc->setPC(tc->readMiscReg(MISCREG_CS_BASE));
-        tc->setNextPC(tc->readPC() + sizeof(MachInst));
+        tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
     }
 
 #else
diff --git a/src/arch/x86/insts/macroop.hh b/src/arch/x86/insts/macroop.hh
index 7ead7bdc2..fcf051a37 100644
--- a/src/arch/x86/insts/macroop.hh
+++ b/src/arch/x86/insts/macroop.hh
@@ -73,7 +73,8 @@ class MacroopBase : public X86StaticInst
 
     StaticInstPtr * microops;
 
-    StaticInstPtr fetchMicroop(MicroPC microPC)
+    StaticInstPtr
+    fetchMicroop(MicroPC microPC) const
     {
         assert(microPC < numMicroops);
         return microops[microPC];
diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh
index 9b0497efc..6fc215452 100644
--- a/src/arch/x86/insts/microop.hh
+++ b/src/arch/x86/insts/microop.hh
@@ -114,6 +114,15 @@ namespace X86ISA
         }
 
         bool checkCondition(uint64_t flags, int condition) const;
+
+        void
+        advancePC(PCState &pcState) const
+        {
+            if (flags[IsLastMicroop])
+                pcState.uEnd();
+            else
+                pcState.uAdvance();
+        }
     };
 }
 
diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh
index 2df5df092..8813f216c 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -158,6 +158,12 @@ namespace X86ISA
                 panic("Tried to pick with unrecognized size %d.\n", size);
             }
         }
+
+        void
+        advancePC(PCState &pcState) const
+        {
+            pcState.advance();
+        }
     };
 }
 
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index de167d1c1..def9b7f9d 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -199,7 +199,7 @@
 #endif
                         0x54: m5panic({{
                             panic("M5 panic instruction called at pc=%#x.\n",
-                                xc->readPC());
+                                xc->pcState().pc());
                         }}, IsNonSpeculative);
                         0x55: m5reserved1({{
                             warn("M5 reserved opcode 1 ignored.\n");
diff --git a/src/arch/x86/isa/formats/unknown.isa b/src/arch/x86/isa/formats/unknown.isa
index 11751e861..1108fd4a4 100644
--- a/src/arch/x86/isa/formats/unknown.isa
+++ b/src/arch/x86/isa/formats/unknown.isa
@@ -47,13 +47,13 @@ output header {{
         /**
          * Class for Unknown/Illegal instructions
          */
-        class Unknown : public StaticInst
+        class Unknown : public X86ISA::X86StaticInst
         {
           public:
 
             // Constructor
             Unknown(ExtMachInst _machInst) :
-                    StaticInst("unknown", _machInst, No_OpClass)
+                    X86ISA::X86StaticInst("unknown", _machInst, No_OpClass)
             {
             }
 
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 9ccea82dd..86ebac174 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -944,8 +944,12 @@ let {{
         code = 'DoubleBits = psrc1 ^ op2;'
 
     class Wrip(WrRegOp, CondRegOp):
-        code = 'RIP = psrc1 + sop2 + CSBase'
-        else_code="RIP = RIP;"
+        code = '''
+        X86ISA::PCState pc = PCS;
+        pc.npc(psrc1 + sop2 + CSBase);
+        PCS = pc;
+        '''
+        else_code = "PCS = PCS;"
 
     class Wruflags(WrRegOp):
         code = 'ccFlagBits = psrc1 ^ op2'
@@ -961,7 +965,10 @@ let {{
         '''
 
     class Rdip(RdRegOp):
-        code = 'DestReg = RIP - CSBase'
+        code = '''
+        X86ISA::PCState pc = PCS;
+        DestReg = pc.npc() - CSBase;
+        '''
 
     class Ruflags(RdRegOp):
         code = 'DestReg = ccFlagBits'
diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa
index 57c44d48c..a3e22b0aa 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -169,15 +169,23 @@ let {{
             return super(Eret, self).getAllocator(microFlags)
 
     iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
-            {"code": "nuIP = target",
-             "else_code": "nuIP = nuIP",
+            {"code": '''
+             X86ISA::PCState pc = PCS;
+             pc.nupc(target);
+             PCS = pc;
+             ''',
+             "else_code": "PCS = PCS",
              "cond_test": "checkCondition(ccFlagBits, cc)"})
     exec_output += SeqOpExecute.subst(iop)
     header_output += SeqOpDeclare.subst(iop)
     decoder_output += SeqOpConstructor.subst(iop)
     iop = InstObjParams("br", "MicroBranch", "SeqOpBase",
-            {"code": "nuIP = target",
-             "else_code": "nuIP = nuIP",
+            {"code": '''
+             X86ISA::PCState pc = PCS;
+             pc.nupc(target);
+             PCS = pc;
+             ''',
+             "else_code": "PCS = PCS",
              "cond_test": "true"})
     exec_output += SeqOpExecute.subst(iop)
     header_output += SeqOpDeclare.subst(iop)
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index d4140e414..25b73a8f2 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -97,9 +97,8 @@ def operands {{
         'FpSrcReg2':     floatReg('src2', 21),
         'FpDestReg':     floatReg('dest', 22),
         'FpData':        floatReg('data', 23),
-        'RIP':           ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
-        'uIP':           ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
-        'nuIP':          ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
+        'PCS':           ('PCState', 'udw', None,
+                          (None, None, 'IsControl'), 50),
         # This holds the condition code portion of the flag register. The
         # nccFlagBits version holds the rest.
         'ccFlagBits':    intReg('INTREG_PSEUDO(0)', 60),
diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
index c5c891be9..6f92cfacf 100644
--- a/src/arch/x86/nativetrace.cc
+++ b/src/arch/x86/nativetrace.cc
@@ -85,7 +85,7 @@ X86NativeTrace::ThreadState::update(ThreadContext *tc)
     r13 = tc->readIntReg(X86ISA::INTREG_R13);
     r14 = tc->readIntReg(X86ISA::INTREG_R14);
     r15 = tc->readIntReg(X86ISA::INTREG_R15);
-    rip = tc->readNextPC();
+    rip = tc->pcState().pc();
     //This should be expanded if x87 registers are considered
     for (int i = 0; i < 8; i++)
         mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh
index 5b38402e0..c06ec18bc 100644
--- a/src/arch/x86/predecoder.hh
+++ b/src/arch/x86/predecoder.hh
@@ -188,11 +188,11 @@ namespace X86ISA
 
         //Use this to give data to the predecoder. This should be used
         //when there is control flow.
-        void moreBytes(Addr pc, Addr fetchPC, MachInst data)
+        void moreBytes(const PCState &pc, Addr fetchPC, MachInst data)
         {
             DPRINTF(Predecoder, "Getting more bytes.\n");
             basePC = fetchPC;
-            offset = (fetchPC >= pc) ? 0 : pc - fetchPC;
+            offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
             fetchChunk = data;
             outOfBytes = false;
             process();
@@ -208,22 +208,26 @@ namespace X86ISA
             return emiIsReady;
         }
 
+        int
+        getInstSize()
+        {
+            int size = basePC + offset - origPC;
+            DPRINTF(Predecoder,
+                    "Calculating the instruction size: "
+                    "basePC: %#x offset: %#x origPC: %#x size: %d\n",
+                    basePC, offset, origPC, size);
+            return size;
+        }
+
         //This returns a constant reference to the ExtMachInst to avoid a copy
-        const ExtMachInst & getExtMachInst()
+        const ExtMachInst &
+        getExtMachInst(X86ISA::PCState &nextPC)
         {
             assert(emiIsReady);
             emiIsReady = false;
+            nextPC.npc(nextPC.pc() + getInstSize());
             return emi;
         }
-
-        int getInstSize()
-        {
-            DPRINTF(Predecoder,
-                    "Calculating the instruction size: "
-                    "basePC: %#x offset: %#x origPC: %#x\n",
-                    basePC, offset, origPC);
-            return basePC + offset - origPC;
-        }
     };
 };
 
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 946a7cbe1..bb875686e 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -116,10 +116,12 @@ X86_64LiveProcess::X86_64LiveProcess(LiveProcessParams *params,
 void
 I386LiveProcess::syscall(int64_t callnum, ThreadContext *tc)
 {
-    Addr eip = tc->readPC();
+    TheISA::PCState pc = tc->pcState();
+    Addr eip = pc.pc();
     if (eip >= vsyscallPage.base &&
             eip < vsyscallPage.base + vsyscallPage.size) {
-        tc->setNextPC(vsyscallPage.base + vsyscallPage.vsysexitOffset);
+        pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset);
+        tc->pcState(pc);
     }
     X86LiveProcess::syscall(callnum, tc);
 }
@@ -645,11 +647,9 @@ X86LiveProcess::argsInit(int pageSize,
     //Set the stack pointer register
     tc->setIntReg(StackPointerReg, stack_min);
 
-    Addr prog_entry = objFile->entryPoint();
     // There doesn't need to be any segment base added in since we're dealing
     // with the flat segmentation model.
-    tc->setPC(prog_entry);
-    tc->setNextPC(prog_entry + sizeof(MachInst));
+    tc->pcState(objFile->entryPoint());
 
     //Align the "stack_min" to a page boundary.
     stack_min = roundDown(stack_min, pageSize);
diff --git a/src/arch/x86/system.cc b/src/arch/x86/system.cc
index ae47b14fd..3fc16e729 100644
--- a/src/arch/x86/system.cc
+++ b/src/arch/x86/system.cc
@@ -320,8 +320,7 @@ X86System::initState()
     cr0.pg = 1;
     tc->setMiscReg(MISCREG_CR0, cr0);
 
-    tc->setPC(tc->getSystemPtr()->kernelEntry);
-    tc->setNextPC(tc->readPC());
+    tc->pcState(tc->getSystemPtr()->kernelEntry);
 
     // We should now be in long mode. Yay!
 
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 71e0b3adb..dbba52af0 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -609,7 +609,7 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
 #else
                 DPRINTF(TLB, "Handling a TLB miss for "
                         "address %#x at pc %#x.\n",
-                        vaddr, tc->readPC());
+                        vaddr, tc->instAddr());
 
                 Process *p = tc->getProcessPtr();
                 TlbEntry newEntry;
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 2a0da7d65..5a208446a 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -42,6 +42,7 @@
 
 #include <iostream>
 
+#include "arch/generic/types.hh"
 #include "base/bitunion.hh"
 #include "base/cprintf.hh"
 #include "base/hashmap.hh"
@@ -221,6 +222,8 @@ namespace X86ISA
         return true;
     }
 
+    typedef GenericISA::UPCState<MachInst> PCState;
+
     struct CoreSpecific {
         int core_type;
     };
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 624e8132f..88d5bfe58 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -72,8 +72,10 @@ void initCPU(ThreadContext *tc, int cpuId)
     InitInterrupt init(0);
     init.invoke(tc);
 
-    tc->setMicroPC(0);
-    tc->setNextMicroPC(1);
+    PCState pc = tc->pcState();
+    pc.upc(0);
+    pc.nupc(1);
+    tc->pcState(pc);
 
     // These next two loops zero internal microcode and implicit registers.
     // They aren't specified by the ISA but are used internally by M5's
@@ -231,8 +233,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     //copy float regs
     copyMiscRegs(src, dest);
 
-    dest->setPC(src->readPC());
-    dest->setNextPC(src->readNextPC());
+    dest->pcState(src->pcState());
 }
 
 void
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 05ce53347..143fde00c 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -46,12 +46,22 @@
 #include "base/misc.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
+#include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 
 class ThreadContext;
 
 namespace X86ISA
 {
+
+    inline PCState
+    buildRetPC(const PCState &curPC, const PCState &callPC)
+    {
+        PCState retPC = callPC;
+        retPC.uEnd();
+        return retPC;
+    }
+
     uint64_t
     getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
 
@@ -86,6 +96,12 @@ namespace X86ISA
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
     void skipFunction(ThreadContext *tc);
+
+    inline void
+    advancePC(PCState &pc, const StaticInstPtr inst)
+    {
+        inst->advancePC(pc);
+    }
 };
 
 #endif // __ARCH_X86_UTILITY_HH__