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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-15 13:39:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-15 13:39:53 -0400 |
| commit | bd583d00f96cd6e8bb0669e2aacc9dfad1eda2b1 (patch) | |
| tree | c7bdbf3c32ea7af6bc2e623cff94ce4b57f470de /src/arch/x86 | |
| parent | 37aab4a1558b223e63cee1e5dd40195ddb7851c0 (diff) | |
| download | gem5-bd583d00f96cd6e8bb0669e2aacc9dfad1eda2b1.tar.xz | |
misc: Appease gcc 5.1
Three minor issues are resolved:
1. Apparently gcc 5.1 does not like negation of booleans followed by
bitwise AND.
2. Somehow the compiler also gets confused and warns about
NoopMachInst being unused (removing it causes compilation errors
though). Most likely a compiler bug.
3. There seems to be a number of instances where loop unrolling causes
false positives for the array-bounds check. For now, switch to
std::array. Potentially we could disable the warning for newer gcc
versions, but switching to std::array is probably a good move in
any case.
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/insts/microop.cc | 8 | ||||
| -rw-r--r-- | src/arch/x86/isa_traits.hh | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/x86/insts/microop.cc b/src/arch/x86/insts/microop.cc index 4f464927a..35ee9efaa 100644 --- a/src/arch/x86/insts/microop.cc +++ b/src/arch/x86/insts/microop.cc @@ -55,7 +55,7 @@ namespace X86ISA case ConditionTests::EZF: return ccflags.ezf; case ConditionTests::SZnZF: - return !(!ccflags.ezf & ccflags.zf); + return !(!ccflags.ezf && ccflags.zf); case ConditionTests::MSTRZ: panic("This condition is not implemented!"); case ConditionTests::STRZ: @@ -63,7 +63,7 @@ namespace X86ISA case ConditionTests::MSTRC: panic("This condition is not implemented!"); case ConditionTests::STRZnEZF: - return !ccflags.ezf & ccflags.zf; + return !ccflags.ezf && ccflags.zf; //And no interrupts or debug traps are waiting case ConditionTests::OF: return ccflags.of; @@ -88,7 +88,7 @@ namespace X86ISA case ConditionTests::NotEZF: return !ccflags.ezf; case ConditionTests::NotSZnZF: - return !ccflags.ezf & ccflags.zf; + return !ccflags.ezf && ccflags.zf; case ConditionTests::NotMSTRZ: panic("This condition is not implemented!"); case ConditionTests::NotSTRZ: @@ -96,7 +96,7 @@ namespace X86ISA case ConditionTests::NotMSTRC: panic("This condition is not implemented!"); case ConditionTests::STRnZnEZF: - return !ccflags.ezf & !ccflags.zf; + return !ccflags.ezf && !ccflags.zf; //And no interrupts or debug traps are waiting case ConditionTests::NotOF: return !ccflags.of; diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index f4fdb59e5..6e5373ca1 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -68,7 +68,7 @@ namespace X86ISA const bool CurThreadInfoImplemented = false; const int CurThreadInfoReg = -1; - const ExtMachInst NoopMachInst = { + const ExtMachInst NoopMachInst M5_VAR_USED = { 0x0, // No legacy prefixes. 0x0, // No rex prefix. { OneByteOpcode, 0x90 }, // One opcode byte, 0x90. |