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authorAlexandru Dutu <alexandru.dutu@amd.com>2016-10-04 13:06:05 -0400
committerAlexandru Dutu <alexandru.dutu@amd.com>2016-10-04 13:06:05 -0400
commit3f0118876f109d0fb94f06687e8d695835a03636 (patch)
treec97e42668120df0729ba9fd04874e9720bc5b1ee /src/arch/x86
parent526b1b7ec8da5b770a345a2ea1b3f7471a533d44 (diff)
downloadgem5-3f0118876f109d0fb94f06687e8d695835a03636.tar.xz
kvm: Adding details to kvm page fault in x86
Adding details, e.g. rip, rsp etc. to the kvm pagefault exit when in SE mode.
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/pseudo_inst.cc21
1 files changed, 19 insertions, 2 deletions
diff --git a/src/arch/x86/pseudo_inst.cc b/src/arch/x86/pseudo_inst.cc
index bd3b5ac7c..f243df73a 100644
--- a/src/arch/x86/pseudo_inst.cc
+++ b/src/arch/x86/pseudo_inst.cc
@@ -29,8 +29,10 @@
*/
#include "arch/x86/pseudo_inst.hh"
+#include "arch/x86/system.hh"
#include "debug/PseudoInst.hh"
#include "sim/process.hh"
+#include "sim/system.hh"
using namespace X86ISA;
@@ -62,8 +64,23 @@ m5PageFault(ThreadContext *tc)
Process *p = tc->getProcessPtr();
if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) {
- panic("Page fault at %#x ", tc->readMiscReg(MISCREG_CR2));
- }
+ SETranslatingPortProxy proxy = tc->getMemProxy();
+ // at this point we should have 6 values on the interrupt stack
+ int size = 6;
+ uint64_t is[size];
+ // reading the interrupt handler stack
+ proxy.readBlob(ISTVirtAddr + PageBytes - size*sizeof(uint64_t),
+ (uint8_t *)&is, sizeof(is));
+ panic("Page fault at addr %#x\n\tInterrupt handler stack:\n"
+ "\tss: %#x\n"
+ "\trsp: %#x\n"
+ "\trflags: %#x\n"
+ "\tcs: %#x\n"
+ "\trip: %#x\n"
+ "\terr_code: %#x\n",
+ tc->readMiscReg(MISCREG_CR2),
+ is[5], is[4], is[3], is[2], is[1], is[0]);
+ }
}
} // namespace X86ISA