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author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:16:15 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:16:15 -0800 |
commit | 6ed47e94644f854baa33d1e9f367cc9eebd99abf (patch) | |
tree | bc19d10504d3ef0bcaa56b6256cfc732897d1531 /src/arch/x86 | |
parent | 15940d06b5f6aabbe917a2a8c4cc4bb1cab991e2 (diff) | |
download | gem5-6ed47e94644f854baa33d1e9f367cc9eebd99abf.tar.xz |
CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.
Diffstat (limited to 'src/arch/x86')
-rw-r--r-- | src/arch/x86/tlb.cc | 22 | ||||
-rw-r--r-- | src/arch/x86/tlb.hh | 12 |
2 files changed, 28 insertions, 6 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 33017a6aa..a34922b44 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -190,7 +190,7 @@ TLB::demapPage(Addr va, uint64_t asn) template<class TlbFault> Fault -TLB::translateAtomic(RequestPtr &req, ThreadContext *tc, +TLB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write, bool execute) { Addr vaddr = req->getVaddr(); @@ -663,17 +663,33 @@ TLB::translateAtomic(RequestPtr &req, ThreadContext *tc, }; Fault -DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write) +DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write) { return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false); } +void +DTB::translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, bool write) +{ + assert(translation); + translation->finish(translateAtomic(req, tc, write), req, tc, write); +} + Fault -ITB::translateAtomic(RequestPtr &req, ThreadContext *tc) +ITB::translateAtomic(RequestPtr req, ThreadContext *tc) { return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true); } +void +ITB::translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation) +{ + assert(translation); + translation->finish(translateAtomic(req, tc), req, tc, false); +} + #if FULL_SYSTEM Tick diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 91bb4a761..56730983a 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -138,8 +138,10 @@ namespace X86ISA EntryList entryList; template<class TlbFault> - Fault translateAtomic(RequestPtr &req, ThreadContext *tc, + Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write, bool execute); + void translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, bool write, bool execute); public: @@ -159,7 +161,9 @@ namespace X86ISA _allowNX = false; } - Fault translateAtomic(RequestPtr &req, ThreadContext *tc); + Fault translateAtomic(RequestPtr req, ThreadContext *tc); + void translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation); friend class DTB; }; @@ -172,7 +176,9 @@ namespace X86ISA { _allowNX = true; } - Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write); + Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write); + void translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, bool write); #if FULL_SYSTEM Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); |