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| author | Jason Lowe-Power <jason@lowepower.com> | 2017-12-13 10:19:04 -0800 |
|---|---|---|
| committer | Jason Lowe-Power <jason@lowepower.com> | 2017-12-14 00:27:59 +0000 |
| commit | 5c41076bd7610d03431fd0dd89bd0fdc7f30d6bd (patch) | |
| tree | ee24cdf5ea368fb808d0b6029313a163c375898b /src/arch/x86 | |
| parent | f07d5069d86e31ecf195664850f79fb00c445bd3 (diff) | |
| download | gem5-5c41076bd7610d03431fd0dd89bd0fdc7f30d6bd.tar.xz | |
misc: Updates for gcc7.2 for x86
GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:
* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878
Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/isa.cc | 4 | ||||
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 3 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index 9dd7fbb52..f092f4418 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -316,7 +316,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) break; case MISCREG_DR4: miscReg = MISCREG_DR6; - /* Fall through to have the same effects as DR6. */ + M5_FALLTHROUGH; case MISCREG_DR6: { DR6 dr6 = regVal[MISCREG_DR6]; @@ -333,7 +333,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) break; case MISCREG_DR5: miscReg = MISCREG_DR7; - /* Fall through to have the same effects as DR7. */ + M5_FALLTHROUGH; case MISCREG_DR7: { DR7 dr7 = regVal[MISCREG_DR7]; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 4fd3b2aa6..2d5ae048a 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -1427,6 +1427,7 @@ let {{ if (bits(newVal, 63, 4)) fault = std::make_shared<GeneralProtection>(0); } + break; default: fault = std::make_shared<GenericISA::M5PanicFault>( "Unrecognized control register %d.\\n", dest); @@ -1528,7 +1529,7 @@ let {{ fault = std::make_shared<GeneralProtection>(selector); break; } - // Fall through on purpose + M5_FALLTHROUGH; case SegIntGateCheck: // Make sure the gate's the right type. if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || |