Address translation: Make the page table more flexible.

The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.

--HG--
extra : convert_revision : 804dcc6320414c2b3ab76a74a15295bd24e1d13d

4 files changed, 33 insertions, 14 deletions

diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index 51c34cebd..936d0357c 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -91,20 +91,10 @@ namespace X86ISA
         }
     };
 
-    static inline Fault genPageTableFault(Addr va)
-    {
-        panic("Page table fault not implemented in x86!\n");
-    }
-
     static inline Fault genMachineCheckFault()
     {
         panic("Machine check fault not implemented in x86!\n");
     }
-
-    static inline Fault genAlignmentFault()
-    {
-        panic("Alignment fault not implemented (or for the most part existant) in x86!\n");
-    }
 };
 
 #endif // __ARCH_X86_FAULTS_HH__
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 364050994..79422998d 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -93,6 +93,7 @@
 #include "base/loader/object_file.hh"
 #include "base/loader/elf_object.hh"
 #include "base/misc.hh"
+#include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "mem/translating_port.hh"
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index bf2458fdf..e29ec58c2 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -60,8 +60,20 @@
 #include "arch/x86/tlb.hh"
 #include "params/X86DTB.hh"
 #include "params/X86ITB.hh"
+#include "sim/serialize.hh"
 
 namespace X86ISA {
+    void
+    TlbEntry::serialize(std::ostream &os)
+    {
+        SERIALIZE_SCALAR(pageStart);
+    }
+
+    void
+    TlbEntry::unserialize(Checkpoint *cp, const std::string &section)
+    {
+        UNSERIALIZE_SCALAR(pageStart);
+    }
 };
 
 X86ISA::ITB *
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index cfd61e3c9..4cf65ac08 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -58,21 +58,37 @@
 #ifndef __ARCH_X86_TLB_HH__
 #define __ARCH_X86_TLB_HH__
 
+#include <iostream>
+#include <string>
+
+#include "sim/host.hh"
 #include "sim/tlb.hh"
 
+class Checkpoint;
+
 namespace X86ISA
 {
-    class ITB : public GenericITB
+    struct TlbEntry
+    {
+        Addr pageStart;
+        TlbEntry() {}
+        TlbEntry(Addr paddr) : pageStart(paddr) {}
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+    };
+
+    class ITB : public GenericITB<false, false>
     {
       public:
-        ITB(const std::string &name) : GenericITB(name)
+        ITB(const std::string &name) : GenericITB<false, false>(name)
         {}
     };
 
-    class DTB : public GenericDTB
+    class DTB : public GenericDTB<false, false>
     {
       public:
-        DTB(const std::string &name) : GenericDTB(name)
+        DTB(const std::string &name) : GenericDTB<false, false>(name)
         {}
     };
 };