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authorSteve Reinhardt <steve.reinhardt@amd.com>2016-01-17 18:27:46 -0800
committerSteve Reinhardt <steve.reinhardt@amd.com>2016-01-17 18:27:46 -0800
commit1b6355c89574c42c5b5f8014b994cf26dae4737d (patch)
tree53ef269f709829563084ba571504c8606ed7d89e /src/arch/x86
parent707275265f188a514d1d5673ed4c8d6495304962 (diff)
downloadgem5-1b6355c89574c42c5b5f8014b994cf26dae4737d.tar.xz
cpu. arch: add initiateMemRead() to ExecContext interface
For historical reasons, the ExecContext interface had a single function, readMem(), that did two different things depending on whether the ExecContext supported atomic memory mode (i.e., AtomicSimpleCPU) or timing memory mode (all the other models). In the former case, it actually performed a memory read; in the latter case, it merely initiated a read access, and the read completion did not happen until later when a response packet arrived from the memory system. This led to some confusing things, including timing accesses being required to provide a pointer for the return data even though that pointer was only used in atomic mode. This patch splits this interface, adding a new initiateMemRead() function to the ExecContext interface to replace the timing-mode use of readMem(). For consistency and clarity, the readMemTiming() helper function in the ISA definitions is renamed to initiateMemRead() as well. For x86, where the access size is passed in explicitly, we can also get rid of the data parameter at this level. For other ISAs, where the access size is determined from the type of the data parameter, we have to keep the parameter for that purpose.
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/isa/formats/monitor_mwait.isa3
-rw-r--r--src/arch/x86/isa/microops/ldstop.isa2
-rw-r--r--src/arch/x86/memhelpers.hh7
3 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa
index b26c1f267..c901ceded 100644
--- a/src/arch/x86/isa/formats/monitor_mwait.isa
+++ b/src/arch/x86/isa/formats/monitor_mwait.isa
@@ -67,10 +67,9 @@ def template MwaitInitiateAcc {{
Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
Trace::InstRecord * traceData) const
{
- uint64_t m = 0; //mem
unsigned s = 0x8; //size
unsigned f = 0; //flags
- readMemTiming(xc, traceData, xc->getAddrMonitor()->vAddr, m, s, f);
+ initiateMemRead(xc, traceData, xc->getAddrMonitor()->vAddr, s, f);
return NoFault;
}
}};
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index a7c201f44..fa8bc6f2b 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -127,7 +127,7 @@ def template MicroLoadInitiateAcc {{
%(ea_code)s;
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
- fault = readMemTiming(xc, traceData, EA, Mem, dataSize, memFlags);
+ fault = initiateMemRead(xc, traceData, EA, dataSize, memFlags);
return fault;
}
diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh
index 640327325..705457d67 100644
--- a/src/arch/x86/memhelpers.hh
+++ b/src/arch/x86/memhelpers.hh
@@ -38,12 +38,13 @@
namespace X86ISA
{
+/// Initiate a read from memory in timing mode.
template <class XC>
Fault
-readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
- uint64_t &mem, unsigned dataSize, unsigned flags)
+initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
+ unsigned dataSize, unsigned flags)
{
- return xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
+ return xc->initiateMemRead(addr, dataSize, flags);
}
static inline uint64_t