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authorAndreas Hansson <andreas.hansson@arm.com>2012-03-19 06:36:09 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-03-19 06:36:09 -0400
commit72538294fb1eb2e4dcd5d818c78bcdf78b0de491 (patch)
treeba95d431b41d54c7c25a3b5e84dfca9707a9feb2 /src/arch/x86
parentadb862103138caf11191da50d34eb4c93295633a (diff)
downloadgem5-72538294fb1eb2e4dcd5d818c78bcdf78b0de491.tar.xz
gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/bios/e820.hh2
-rw-r--r--src/arch/x86/emulenv.hh2
-rw-r--r--src/arch/x86/faults.hh2
-rw-r--r--src/arch/x86/isa/macroop.isa2
-rw-r--r--src/arch/x86/isa_traits.hh2
-rw-r--r--src/arch/x86/locked_mem.hh2
-rw-r--r--src/arch/x86/mmapped_ipr.hh2
-rw-r--r--src/arch/x86/nativetrace.cc2
-rw-r--r--src/arch/x86/predecoder.hh2
-rw-r--r--src/arch/x86/regs/float.hh2
-rw-r--r--src/arch/x86/regs/int.hh2
-rw-r--r--src/arch/x86/regs/misc.hh2
-rw-r--r--src/arch/x86/regs/segment.hh2
-rw-r--r--src/arch/x86/tlb.cc2
-rw-r--r--src/arch/x86/types.hh2
-rw-r--r--src/arch/x86/utility.hh2
-rw-r--r--src/arch/x86/vtophys.hh2
17 files changed, 17 insertions, 17 deletions
diff --git a/src/arch/x86/bios/e820.hh b/src/arch/x86/bios/e820.hh
index b61708050..5348481b6 100644
--- a/src/arch/x86/bios/e820.hh
+++ b/src/arch/x86/bios/e820.hh
@@ -77,6 +77,6 @@ namespace X86ISA
void writeTo(PortProxy& proxy, Addr countAddr, Addr addr);
};
-};
+}
#endif // __ARCH_X86_BIOS_E820_HH__
diff --git a/src/arch/x86/emulenv.hh b/src/arch/x86/emulenv.hh
index ac707d808..719447bf8 100644
--- a/src/arch/x86/emulenv.hh
+++ b/src/arch/x86/emulenv.hh
@@ -71,6 +71,6 @@ namespace X86ISA
void doModRM(const ExtMachInst & machInst);
void setSeg(const ExtMachInst & machInst);
};
-};
+}
#endif // __ARCH_X86_TYPES_HH__
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index 94a2ffcc2..637f131e0 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -419,6 +419,6 @@ namespace X86ISA
return true;
}
};
-};
+}
#endif // __ARCH_X86_FAULTS_HH__
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index f05015834..94b17ff4c 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -89,7 +89,7 @@ def template MacroDeclare {{
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
- };
+ }
}};
def template MacroDisassembly {{
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 09a280215..34c5b5ebc 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -85,6 +85,6 @@ namespace X86ISA
SixtyFourBitMode // Behave as if we're in 64 bit
// mode (this doesn't actually matter).
};
-};
+}
#endif // __ARCH_X86_ISATRAITS_HH__
diff --git a/src/arch/x86/locked_mem.hh b/src/arch/x86/locked_mem.hh
index e1d289ee9..496486997 100644
--- a/src/arch/x86/locked_mem.hh
+++ b/src/arch/x86/locked_mem.hh
@@ -53,6 +53,6 @@ namespace X86ISA
{
return true;
}
-};
+}
#endif // __ARCH_X86_LOCKEDMEM_HH__
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index 054f280a8..4c3292388 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -78,6 +78,6 @@ namespace X86ISA
xc->setMiscReg(index, gtoh(data));
return xc->getCpuPtr()->ticks(1);
}
-};
+}
#endif // __ARCH_X86_MMAPPEDIPR_HH__
diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
index 557508ee7..b7d903a1b 100644
--- a/src/arch/x86/nativetrace.cc
+++ b/src/arch/x86/nativetrace.cc
@@ -197,4 +197,4 @@ Trace::X86NativeTrace *
X86NativeTraceParams::create()
{
return new Trace::X86NativeTrace(this);
-};
+}
diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh
index 49938dd16..f7c63684d 100644
--- a/src/arch/x86/predecoder.hh
+++ b/src/arch/x86/predecoder.hh
@@ -234,6 +234,6 @@ namespace X86ISA
return emi;
}
};
-};
+}
#endif // __ARCH_X86_PREDECODER_HH__
diff --git a/src/arch/x86/regs/float.hh b/src/arch/x86/regs/float.hh
index 5ac33c40f..bdcffb86b 100644
--- a/src/arch/x86/regs/float.hh
+++ b/src/arch/x86/regs/float.hh
@@ -150,6 +150,6 @@ namespace X86ISA
{
return FLOATREG_FPR((top + index + 8) % 8);
}
-};
+}
#endif // __ARCH_X86_FLOATREGS_HH__
diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh
index 2a1371051..0a682ef54 100644
--- a/src/arch/x86/regs/int.hh
+++ b/src/arch/x86/regs/int.hh
@@ -178,6 +178,6 @@ namespace X86ISA
index = (index - 4) | foldBit;
return (IntRegIndex)index;
}
-};
+}
#endif // __ARCH_X86_INTREGS_HH__
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 74c6bd133..24420e8d5 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -915,6 +915,6 @@ namespace X86ISA
Bitfield<11> enable;
Bitfield<8> bsp;
EndBitUnion(LocalApicBase)
-};
+}
#endif // __ARCH_X86_INTREGS_HH__
diff --git a/src/arch/x86/regs/segment.hh b/src/arch/x86/regs/segment.hh
index 737934152..cebb1235b 100644
--- a/src/arch/x86/regs/segment.hh
+++ b/src/arch/x86/regs/segment.hh
@@ -63,6 +63,6 @@ namespace X86ISA
NUM_SEGMENTREGS
};
-};
+}
#endif // __ARCH_X86_SEGMENTREGS_HH__
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index b7d0b828c..10ef217e1 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -384,7 +384,7 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
}
}
return NoFault;
-};
+}
Fault
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 8b1469c2d..c7e824fb7 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -278,7 +278,7 @@ namespace X86ISA
}
};
-};
+}
namespace __hash_namespace {
template<>
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index f120ea6c7..f3b0d3fa1 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -105,6 +105,6 @@ namespace X86ISA
return 0;
}
-};
+}
#endif // __ARCH_X86_UTILITY_HH__
diff --git a/src/arch/x86/vtophys.hh b/src/arch/x86/vtophys.hh
index 10522313c..7b987f6df 100644
--- a/src/arch/x86/vtophys.hh
+++ b/src/arch/x86/vtophys.hh
@@ -50,6 +50,6 @@ namespace X86ISA
Addr vtophys(Addr vaddr);
Addr vtophys(ThreadContext *tc, Addr vaddr);
-};
+}
#endif // __ARCH_X86_VTOPHYS_HH__