X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.

--HG--
extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af

9 files changed, 464 insertions, 129 deletions

diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index f4a8782f2..623d61aec 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -88,6 +88,7 @@ Import('*')
 if env['TARGET_ISA'] == 'x86':
     Source('emulenv.cc')
     Source('floatregfile.cc')
+    Source('faults.cc')
     Source('insts/microfpop.cc')
     Source('insts/microldstop.cc')
     Source('insts/microop.cc')
@@ -95,6 +96,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('insts/static_inst.cc')
     Source('intregfile.cc')
     Source('miscregfile.cc')
+    Source('pagetable.cc')
     Source('predecoder.cc')
     Source('predecoder_tables.cc')
     Source('regfile.cc')
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index f16408e63..ce4db4f4c 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -58,18 +58,18 @@ from m5.params import *
 class X86TLB(SimObject):
     type = 'X86TLB'
     abstract = True
-    #size = Param.Int("TLB size")
+    size = Param.Int("TLB size")
 
 class X86DTB(X86TLB):
     type = 'X86DTB'
     cxx_namespace = 'X86ISA'
     cxx_class = 'DTB'
 
-    #size = 64
+    size = 64
 
 class X86ITB(X86TLB):
     type = 'X86ITB'
     cxx_namespace = 'X86ISA'
     cxx_class = 'ITB'
 
-    #size = 64
+    size = 64
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
new file mode 100644
index 000000000..124dcf41e
--- /dev/null
+++ b/src/arch/x86/faults.cc
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2003-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use.  Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ *     Director of Intellectual Property Licensing
+ *     Office of Strategy and Technology
+ *     Hewlett-Packard Company
+ *     1501 Page Mill Road
+ *     Palo Alto, California  94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.  Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.  Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.  No right of
+ * sublicense is granted herewith.  Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses.  Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/faults.hh"
+#include "base/trace.hh"
+#include "config/full_system.hh"
+#include "cpu/thread_context.hh"
+#if !FULL_SYSTEM
+#include "arch/x86/isa_traits.hh"
+#include "mem/page_table.hh"
+#include "sim/process.hh"
+#endif
+
+namespace X86ISA
+{
+#if FULL_SYSTEM
+    void X86Trap::invoke(TheeadContext * tc)
+    {
+        panic("X86 faults are not implemented!");
+    }
+
+    void X86Abort::invoke(TheeadContext * tc)
+    {
+        panic("X86 faults are not implemented!");
+    }
+
+    void X86Interrupt::invoke(TheeadContext * tc)
+    {
+        panic("X86 faults are not implemented!");
+    }
+#else // !FULL_SYSTEM
+    void FakeITLBFault::invoke(ThreadContext * tc)
+    {
+        DPRINTF(TLB, "Invoking an ITLB fault for address %#x at pc %#x.\n",
+                vaddr, tc->readPC());
+        Process *p = tc->getProcessPtr();
+        Addr paddr;
+        bool success = p->pTable->translate(vaddr, paddr);
+        if(!success) {
+            panic("Tried to execute unmapped address %#x.\n", vaddr);
+        } else {
+            TlbEntry entry;
+            entry.pageStart = p->pTable->pageAlign(paddr);
+            entry.writeable = false;
+            entry.user = true;
+            entry.uncacheable = false;
+            entry.global = false;
+            entry.patBit = 0;
+            entry.noExec = false;
+            entry.size = PageBytes;
+            Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+            DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
+            tc->getITBPtr()->insert(alignedVaddr, entry);
+        }
+    }
+
+    void FakeDTLBFault::invoke(ThreadContext * tc)
+    {
+        DPRINTF(TLB, "Invoking an DTLB fault for address %#x at pc %#x.\n",
+                vaddr, tc->readPC());
+        Process *p = tc->getProcessPtr();
+        Addr paddr;
+        bool success = p->pTable->translate(vaddr, paddr);
+        if(!success) {
+            p->checkAndAllocNextPage(vaddr);
+            success = p->pTable->translate(vaddr, paddr);
+        }
+        if(!success) {
+            panic("Tried to access unmapped address %#x.\n", vaddr);
+        } else {
+            TlbEntry entry;
+            entry.pageStart = p->pTable->pageAlign(paddr);
+            entry.writeable = true;
+            entry.user = true;
+            entry.uncacheable = false;
+            entry.global = false;
+            entry.patBit = 0;
+            entry.noExec = true;
+            entry.size = PageBytes;
+            Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+            DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
+            tc->getDTBPtr()->insert(alignedVaddr, entry);
+        }
+    }
+#endif
+} // namespace X86ISA
+
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index 31bb686ed..0579be9b5 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -111,10 +111,7 @@ namespace X86ISA
         {}
 
 #if FULL_SYSTEM
-        void invoke(ThreadContext * tc)
-        {
-            panic("X86 faults are not implemented!");
-        }
+        void invoke(ThreadContext * tc);
 #endif
     };
 
@@ -127,10 +124,7 @@ namespace X86ISA
         {}
 
 #if FULL_SYSTEM
-        void invoke(ThreadContext * tc)
-        {
-            panic("X86 faults are not implemented!");
-        }
+        void invoke(ThreadContext * tc);
 #endif
     };
 
@@ -143,10 +137,7 @@ namespace X86ISA
         {}
 
 #if FULL_SYSTEM
-        void invoke(ThreadContext * tc)
-        {
-            panic("X86 faults are not implemented!");
-        }
+        void invoke(ThreadContext * tc);
 #endif
     };
 
@@ -372,18 +363,44 @@ namespace X86ISA
     // the tlb on a miss and are to take the place of a hardware table walker.
     class FakeITLBFault : public X86Fault
     {
+#if !FULL_SYSTEM
+      protected:
+        Addr vaddr;
+      public:
+        FakeITLBFault(Addr _vaddr) :
+            X86Fault("fake instruction tlb fault", "itlb"),
+            vaddr(_vaddr)
+#else
       public:
         FakeITLBFault() :
             X86Fault("fake instruction tlb fault", "itlb")
+#endif
         {}
+
+#if !FULL_SYSTEM
+        void invoke(ThreadContext * tc);
+#endif
     };
 
     class FakeDTLBFault : public X86Fault
     {
+#if !FULL_SYSTEM
+      protected:
+        Addr vaddr;
+      public:
+        FakeDTLBFault(Addr _vaddr) :
+            X86Fault("fake data tlb fault", "dtlb"),
+            vaddr(_vaddr)
+#else
       public:
         FakeDTLBFault() :
             X86Fault("fake data tlb fault", "dtlb")
+#endif
         {}
+
+#if !FULL_SYSTEM
+        void invoke(ThreadContext * tc);
+#endif
     };
 };
 
diff --git a/src/arch/x86/pagetable.cc b/src/arch/x86/pagetable.cc
new file mode 100644
index 000000000..49aaab068
--- /dev/null
+++ b/src/arch/x86/pagetable.cc
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use.  Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ *     Director of Intellectual Property Licensing
+ *     Office of Strategy and Technology
+ *     Hewlett-Packard Company
+ *     1501 Page Mill Road
+ *     Palo Alto, California  94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.  Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.  Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.  No right of
+ * sublicense is granted herewith.  Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses.  Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/pagetable.hh"
+#include "sim/serialize.hh"
+
+namespace X86ISA
+{
+
+void
+TlbEntry::serialize(std::ostream &os)
+{
+}
+
+void
+TlbEntry::unserialize(Checkpoint *cp, const std::string &section)
+{
+}
+
+}
diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index 8ca179c86..aaf82ed70 100644
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -58,9 +58,14 @@
 #ifndef __ARCH_X86_PAGETABLE_HH__
 #define __ARCH_X86_PAGETABLE_HH__
 
+#include <iostream>
+#include <string>
+
 #include "sim/host.hh"
 #include "base/misc.hh"
 
+class Checkpoint;
+
 namespace X86ISA
 {
     struct VAddr
@@ -68,8 +73,37 @@ namespace X86ISA
         VAddr(Addr a) { panic("not implemented yet."); }
     };
 
-    class PageTableEntry
+    struct TlbEntry
     {
+        // The base of the physical page.
+        Addr pageStart;
+        // Read permission is always available, assuming it isn't blocked by
+        // other mechanisms.
+        bool writeable;
+        // Whether this page is accesible without being in supervisor mode.
+        bool user;
+        // Whether to use write through or write back. M5 ignores this and
+        // lets the caches handle the writeback policy.
+        //bool pwt;
+        // Whether the page is cacheable or not.
+        bool uncacheable;
+        // Whether or not to kick this page out on a write to CR3.
+        bool global;
+        // A bit used to form an index into the PAT table.
+        bool patBit;
+        // Whether or not memory on this page can be executed.
+        bool noExec;
+
+        // The beginning of the virtual page this entry maps.
+        Addr vaddr;
+        // The size of the page this entry represents.
+        Addr size;
+
+        TlbEntry() {}
+        TlbEntry(Addr paddr) : pageStart(paddr) {}
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
     };
 }
 
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index ad23cb7e4..f4a55129b 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -59,8 +59,7 @@
 
 #include "config/full_system.hh"
 
-#if FULL_SYSTEM
-
+#include "arch/x86/pagetable.hh"
 #include "arch/x86/tlb.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
@@ -72,21 +71,114 @@
 
 namespace X86ISA {
 
-TLB::TLB(const Params *p) : SimObject(p)
+TLB::TLB(const Params *p) : SimObject(p), size(p->size)
+{
+    tlb = new TlbEntry[size];
+    std::memset(tlb, 0, sizeof(TlbEntry) * size);
+
+    for (int x = 0; x < size; x++)
+        freeList.push_back(&tlb[x]);
+}
+
+void
+TLB::insert(Addr vpn, TlbEntry &entry)
+{
+    //TODO Deal with conflicting entries
+
+    TlbEntry *newEntry = NULL;
+    if (!freeList.empty()) {
+        newEntry = freeList.front();
+        freeList.pop_front();
+    } else {
+        newEntry = entryList.back();
+        entryList.pop_back();
+    }
+    *newEntry = entry;
+    newEntry->vaddr = vpn;
+    entryList.push_front(newEntry);
+}
+
+TlbEntry *
+TLB::lookup(Addr va, bool update_lru)
+{
+    //TODO make this smarter at some point
+    EntryList::iterator entry;
+    for (entry = entryList.begin(); entry != entryList.end(); entry++) {
+        if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
+            DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
+                    "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
+            TlbEntry *e = *entry;
+            if (update_lru) {
+                entryList.erase(entry);
+                entryList.push_front(e);
+            }
+            return e;
+        }
+    }
+    return NULL;
+}
+
+void
+TLB::invalidateAll()
+{
+}
+
+void
+TLB::invalidateNonGlobal()
+{
+}
+
+void
+TLB::demapPage(Addr va)
 {
 }
 
 Fault
 ITB::translate(RequestPtr &req, ThreadContext *tc)
 {
+    Addr vaddr = req->getVaddr();
+    // Check against the limit of the CS segment, and permissions.
+    // The vaddr already has the segment base applied.
+    TlbEntry *entry = lookup(vaddr);
+    if (!entry) {
+#if FULL_SYSTEM
+        return new FakeITLBFault();
+#else
+        return new FakeITLBFault(vaddr);
+#endif
+    } else {
+        Addr paddr = entry->pageStart | (vaddr & mask(12));
+        DPRINTF(TLB, "Translated %#x to %#x\n", vaddr, paddr);
+        req->setPaddr(paddr);
+    }
+
     return NoFault;
 }
 
-
-
 Fault
 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 {
+    Addr vaddr = req->getVaddr();
+    uint32_t flags = req->getFlags();
+    bool storeCheck = flags & StoreCheck;
+    int seg = flags & (mask(NUM_SEGMENTREGS));
+
+    //XXX Junk code to surpress the warning
+    if (storeCheck) seg = seg;
+
+    // Check the limit of the segment "seg", and permissions.
+    // The vaddr already has the segment base applied.
+    TlbEntry *entry = lookup(vaddr);
+    if (!entry) {
+#if FULL_SYSTEM
+        return new FakeDTLBFault();
+#else
+        return new FakeDTLBFault(vaddr);
+#endif
+    } else {
+        Addr paddr = entry->pageStart | (vaddr & mask(12));
+        req->setPaddr(paddr);
+    }
     return NoFault;
 };
 
@@ -130,31 +222,6 @@ DTB::unserialize(Checkpoint *cp, const std::string &section)
 
 /* end namespace X86ISA */ }
 
-#else
-
-#include <cstring>
-
-#include "arch/x86/tlb.hh"
-#include "params/X86DTB.hh"
-#include "params/X86ITB.hh"
-#include "sim/serialize.hh"
-
-namespace X86ISA {
-    void
-    TlbEntry::serialize(std::ostream &os)
-    {
-        SERIALIZE_SCALAR(pageStart);
-    }
-
-    void
-    TlbEntry::unserialize(Checkpoint *cp, const std::string &section)
-    {
-        UNSERIALIZE_SCALAR(pageStart);
-    }
-};
-
-#endif
-
 X86ISA::ITB *
 X86ITBParams::create()
 {
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 24373c623..720b03b98 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -58,11 +58,11 @@
 #ifndef __ARCH_X86_TLB_HH__
 #define __ARCH_X86_TLB_HH__
 
-#include "config/full_system.hh"
-
-#if FULL_SYSTEM
+#include <list>
 
-#include "arch/segmentregs.hh"
+#include "arch/x86/pagetable.hh"
+#include "arch/x86/segmentregs.hh"
+#include "config/full_system.hh"
 #include "mem/request.hh"
 #include "params/X86DTB.hh"
 #include "params/X86ITB.hh"
@@ -76,102 +76,75 @@ namespace X86ISA
 {
     static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
 
-    struct TlbEntry
-    {
-        Addr pageStart;
-        TlbEntry() {}
-        TlbEntry(Addr paddr) : pageStart(paddr) {}
-
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
-    };
-
-class TLB : public SimObject
-{
-  public:
-    typedef X86TLBParams Params;
-    TLB(const Params *p);
-
-    void dumpAll();
-
-    // Checkpointing
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
-};
-
-class ITB : public TLB
-{
-  public:
-    typedef X86ITBParams Params;
-    ITB(const Params *p) : TLB(p)
-    {
-    }
-
-    Fault translate(RequestPtr &req, ThreadContext *tc);
-
-    friend class DTB;
-};
-
-class DTB : public TLB
-{
-  public:
-    typedef X86DTBParams Params;
-    DTB(const Params *p) : TLB(p)
+    class TLB : public SimObject
     {
-    }
-
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
-#if FULL_SYSTEM
-    Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
-    Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+#if !FULL_SYSTEM
+      protected:
+        friend class FakeITLBFault;
+        friend class FakeDTLBFault;
 #endif
+      public:
+        typedef X86TLBParams Params;
+        TLB(const Params *p);
 
-    // Checkpointing
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
-};
+        void dumpAll();
 
-}
+        TlbEntry *lookup(Addr va, bool update_lru = true);
 
-#else
+      protected:
+        int size;
 
-#include <iostream>
+        TlbEntry * tlb;
 
-#include "arch/x86/segmentregs.hh"
-#include "sim/host.hh"
-#include "sim/tlb.hh"
+        typedef std::list<TlbEntry *> EntryList;
+        EntryList freeList;
+        EntryList entryList;
 
-class Checkpoint;
+        void insert(Addr vpn, TlbEntry &entry);
 
-namespace X86ISA
-{
-    static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
+        void invalidateAll();
 
-    struct TlbEntry
-    {
-        Addr pageStart;
-        TlbEntry() {}
-        TlbEntry(Addr paddr) : pageStart(paddr) {}
+        void invalidateNonGlobal();
 
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
+        void demapPage(Addr va);
+
+      public:
+        // Checkpointing
+        virtual void serialize(std::ostream &os);
+        virtual void unserialize(Checkpoint *cp, const std::string &section);
     };
 
-    class ITB : public GenericTLB
+    class ITB : public TLB
     {
       public:
-        ITB(const Params *p) : GenericTLB(p)
-        {}
+        typedef X86ITBParams Params;
+        ITB(const Params *p) : TLB(p)
+        {
+        }
+
+        Fault translate(RequestPtr &req, ThreadContext *tc);
+
+        friend class DTB;
     };
 
-    class DTB : public GenericTLB
+    class DTB : public TLB
     {
       public:
-        DTB(const Params *p) : GenericTLB(p)
-        {}
-    };
-};
+        typedef X86DTBParams Params;
+        DTB(const Params *p) : TLB(p)
+        {
+        }
 
+        Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+#if FULL_SYSTEM
+        Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
+        Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
 #endif
 
+        // Checkpointing
+        virtual void serialize(std::ostream &os);
+        virtual void unserialize(Checkpoint *cp, const std::string &section);
+    };
+}
+
 #endif // __ARCH_X86_TLB_HH__
diff --git a/src/arch/x86/vtophys.hh b/src/arch/x86/vtophys.hh
index 00d0f9499..be5e2700f 100644
--- a/src/arch/x86/vtophys.hh
+++ b/src/arch/x86/vtophys.hh
@@ -68,9 +68,6 @@ class FunctionalPort;
 namespace X86ISA
 {
 
-PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, X86ISA::VAddr vaddr);
-
 Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);