misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.

8 files changed, 16 insertions, 16 deletions

diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index d42751d21..2e5e83764 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -32,6 +32,7 @@
 #define __ARCH_X86_DECODER_HH__
 
 #include <cassert>
+#include <unordered_map>
 #include <vector>
 
 #include "arch/x86/regs/misc.hh"
@@ -223,11 +224,11 @@ class Decoder
 
     typedef DecodeCache::AddrMap<Decoder::InstBytes> DecodePages;
     DecodePages *decodePages;
-    typedef m5::hash_map<CacheKey, DecodePages *> AddrCacheMap;
+    typedef std::unordered_map<CacheKey, DecodePages *> AddrCacheMap;
     AddrCacheMap addrCacheMap;
 
     DecodeCache::InstMap *instMap;
-    typedef m5::hash_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
+    typedef std::unordered_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
     static InstCacheMap instCacheMap;
 
   public:
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 272cfea44..b1bdbf10f 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -293,8 +293,8 @@ class Interrupts : public BasicPioDevice, IntDevice
     /*
      * Serialization.
      */
-    void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
-    void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+    void serialize(CheckpointOut &cp) const override;
+    void unserialize(CheckpointIn &cp) override;
 
     /*
      * Old functions needed for compatability but which will be phased out
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 88f4980ae..90ab619cc 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -97,8 +97,8 @@ namespace X86ISA
             return reg;
         }
 
-        void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
-        void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;
 
         void startup(ThreadContext *tc);
 
diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index 3345366d0..1361109d5 100644
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -149,8 +149,8 @@ namespace X86ISA
             return (1 << logBytes);
         }
 
-        void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
-        void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;
     };
 
     /** The size of each level of the page table expressed in base 2
diff --git a/src/arch/x86/regs/msr.hh b/src/arch/x86/regs/msr.hh
index a2ae5c69a..f273a8227 100644
--- a/src/arch/x86/regs/msr.hh
+++ b/src/arch/x86/regs/msr.hh
@@ -31,14 +31,15 @@
 #ifndef __ARCH_X86_REG_MSR_HH__
 #define __ARCH_X86_REG_MSR_HH__
 
+#include <unordered_map>
+
 #include "arch/x86/regs/misc.hh"
-#include "base/hashmap.hh"
 #include "base/types.hh"
 
 namespace X86ISA
 {
 
-typedef m5::hash_map<Addr, MiscRegIndex> MsrMap;
+typedef std::unordered_map<Addr, MiscRegIndex> MsrMap;
 
 /**
  * Map between MSR addresses and their corresponding misc registers.
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 83ec7cc59..6e3eb2eee 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -148,8 +148,8 @@ namespace X86ISA
         TlbEntry * insert(Addr vpn, TlbEntry &entry);
 
         // Checkpointing
-        void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
-        void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;
 
         /**
          * Get the table walker master port. This is used for
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 88b000b6e..99e2c826c 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -45,7 +45,6 @@
 #include "arch/generic/types.hh"
 #include "base/bitunion.hh"
 #include "base/cprintf.hh"
-#include "base/hashmap.hh"
 #include "base/types.hh"
 #include "sim/serialize.hh"
 
@@ -346,7 +345,7 @@ namespace X86ISA
 
 }
 
-__hash_namespace_begin
+namespace std {
     template<>
     struct hash<X86ISA::ExtMachInst> {
         size_t operator()(const X86ISA::ExtMachInst &emi) const {
@@ -362,7 +361,7 @@ __hash_namespace_begin
                     emi.stackSize ^ emi.dispSize;
         };
     };
-__hash_namespace_end
+}
 
 // These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
 // and UNSERIALIZE_SCALAR.
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 9be66d8d2..87bed9762 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -42,7 +42,6 @@
 
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/types.hh"
-#include "base/hashmap.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"