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author | Gabe Black <gblack@eecs.umich.edu> | 2007-03-05 16:09:09 +0000 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-03-05 16:09:09 +0000 |
commit | 78e5406f1958e0a25b832aab6e3c2842641d595f (patch) | |
tree | 4d46ac831adf453045920c7f047a766272b4480f /src/arch/x86 | |
parent | 05ba90b7268089cab46f35c7808502055c18c4d7 (diff) | |
download | gem5-78e5406f1958e0a25b832aab6e3c2842641d595f.tar.xz |
Stub implementation for x86.
--HG--
extra : convert_revision : 3eccbf699bb62139a06a9b249e56bd205bc316ed
Diffstat (limited to 'src/arch/x86')
-rw-r--r-- | src/arch/x86/mmaped_ipr.hh | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/src/arch/x86/mmaped_ipr.hh b/src/arch/x86/mmaped_ipr.hh index f2a447851..a33a3f4f0 100644 --- a/src/arch/x86/mmaped_ipr.hh +++ b/src/arch/x86/mmaped_ipr.hh @@ -58,10 +58,33 @@ #ifndef __ARCH_X86_MMAPEDIPR_HH__ #define __ARCH_X86_MMAPEDIPR_HH__ -#error X86 is not yet supported! +/** + * @file + * + * ISA-specific helper functions for memory mapped IPR accesses. + */ + +#include "config/full_system.hh" +#include "cpu/thread_context.hh" +#include "mem/packet.hh" namespace X86ISA { + inline Tick + handleIprRead(ThreadContext *xc, Packet *pkt) + { +#if !FULL_SYSTEM + panic("Shouldn't have a memory mapped register in SE\n"); +#endif + } + + inline Tick + handleIprWrite(ThreadContext *xc, Packet *pkt) + { +#if !FULL_SYSTEM + panic("Shouldn't have a memory mapped register in SE\n"); +#endif + } }; #endif // __ARCH_X86_MMAPEDIPR_HH__ |