Registers: Add a registers.hh file as an ISA switched header.

This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh

11 files changed, 94 insertions, 195 deletions

diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index f500089f3..1cb0edaf2 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -99,7 +99,6 @@ if env['TARGET_ISA'] == 'x86':
     Source('pagetable.cc')
     Source('predecoder.cc')
     Source('predecoder_tables.cc')
-    Source('regfile.cc')
     Source('remote_gdb.cc')
     Source('tlb.cc')
     Source('utility.cc')
diff --git a/src/arch/x86/emulenv.hh b/src/arch/x86/emulenv.hh
index cdb1bf863..bcefd4456 100644
--- a/src/arch/x86/emulenv.hh
+++ b/src/arch/x86/emulenv.hh
@@ -60,6 +60,7 @@
 
 #include "arch/x86/intregs.hh"
 #include "arch/x86/segmentregs.hh"
+#include "arch/x86/registers.hh"
 #include "arch/x86/types.hh"
 
 namespace X86ISA
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 8626f117a..93685cd9f 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -103,7 +103,7 @@ output header {{
 #include "arch/x86/insts/microregop.hh"
 #include "arch/x86/insts/static_inst.hh"
 #include "arch/x86/isa_traits.hh"
-#include "arch/x86/regfile.hh"
+#include "arch/x86/registers.hh"
 #include "arch/x86/types.hh"
 #include "base/misc.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 2b549bb4a..9f1b7b7c4 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -58,8 +58,6 @@
 #ifndef __ARCH_X86_ISATRAITS_HH__
 #define __ARCH_X86_ISATRAITS_HH__
 
-#include "arch/x86/intregs.hh"
-#include "arch/x86/max_inst_regs.hh"
 #include "arch/x86/types.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/types.hh"
@@ -73,8 +71,6 @@ namespace X86ISA
     //This makes sure the little endian version of certain functions
     //are used.
     using namespace LittleEndianGuest;
-    using X86ISAInst::MaxInstSrcRegs;
-    using X86ISAInst::MaxInstDestRegs;
 
     // X86 does not have a delay slot
 #define ISA_HAS_DELAY_SLOT 0
@@ -83,36 +79,6 @@ namespace X86ISA
     //XXX This needs to be set to an intermediate instruction struct
     //which encodes this instruction
 
-    // These enumerate all the registers for dependence tracking.
-    enum DependenceTags {
-        //There are 16 microcode registers at the moment. This is an
-        //unusually large constant to make sure there isn't overflow.
-        FP_Base_DepTag = 128,
-        Ctrl_Base_DepTag =
-            FP_Base_DepTag +
-            //mmx/x87 registers
-            8 +
-            //xmm registers
-            16 * 2 +
-            //The microcode fp registers
-            8 +
-            //The indices that are mapped over the fp stack
-            8
-    };
-
-    // semantically meaningful register indices
-    //There is no such register in X86
-    const int ZeroReg = NUM_INTREGS;
-    const int StackPointerReg = INTREG_RSP;
-    //X86 doesn't seem to have a link register
-    const int ReturnAddressReg = 0;
-    const int ReturnValueReg = INTREG_RAX;
-    const int FramePointerReg = INTREG_RBP;
-
-    // Some OS syscalls use a second register (rdx) to return a second
-    // value
-    const int SyscallPseudoReturnReg = INTREG_RDX;
-
     //4k. This value is not constant on x86.
     const int LogVMPageSize = 12;
     const int VMPageSize = (1 << LogVMPageSize);
diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index 1d109ae27..b7d72d594 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -57,7 +57,7 @@
 
 #include "arch/x86/isa_traits.hh"
 #include "arch/x86/linux/process.hh"
-#include "arch/x86/regfile.hh"
+#include "arch/x86/registers.hh"
 
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh
index f2329b7b4..8e8adc63b 100644
--- a/src/arch/x86/miscregfile.hh
+++ b/src/arch/x86/miscregfile.hh
@@ -92,7 +92,7 @@
 
 #include "arch/x86/faults.hh"
 #include "arch/x86/miscregs.hh"
-#include "arch/x86/types.hh"
+#include "arch/x86/registers.hh"
 #include "base/types.hh"
 
 class Checkpoint;
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
deleted file mode 100644
index 67ef0b128..000000000
--- a/src/arch/x86/regfile.cc
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (c) 2003-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-/*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
- * All rights reserved.
- *
- * Redistribution and use of this software in source and binary forms,
- * with or without modification, are permitted provided that the
- * following conditions are met:
- *
- * The software must be used only for Non-Commercial Use which means any
- * use which is NOT directed to receiving any direct monetary
- * compensation for, or commercial advantage from such use.  Illustrative
- * examples of non-commercial use are academic research, personal study,
- * teaching, education and corporate research & development.
- * Illustrative examples of commercial use are distributing products for
- * commercial advantage and providing services using the software for
- * commercial advantage.
- *
- * If you wish to use this software or functionality therein that may be
- * covered by patents for commercial use, please contact:
- *     Director of Intellectual Property Licensing
- *     Office of Strategy and Technology
- *     Hewlett-Packard Company
- *     1501 Page Mill Road
- *     Palo Alto, California  94304
- *
- * Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.  Redistributions
- * in binary form must reproduce the above copyright notice, this list of
- * conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.  Neither the name of
- * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.  No right of
- * sublicense is granted herewith.  Derivatives of the software and
- * output created using the software may be prepared, but only for
- * Non-Commercial Uses.  Derivatives of the software may be shared with
- * others provided: (i) the others agree to abide by the list of
- * conditions herein which includes the Non-Commercial Use restrictions;
- * and (ii) such Derivatives of the software include the above copyright
- * notice to acknowledge the contribution from this software where
- * applicable, this list of conditions and the disclaimer below.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/x86/miscregs.hh"
-#include "arch/x86/regfile.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-
-void
-X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    warn("copyMiscRegs is naively implemented for x86\n");
-    for (int i = 0; i < NUM_MISCREGS; ++i) {
-        if ( ( i != MISCREG_CR1 &&
-             !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
-             !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
-             continue;
-        }
-        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
-    }
-}
-
-void
-X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("copyRegs not implemented for x86!\n");
-    //copy int regs
-    //copy float regs
-    copyMiscRegs(src, dest);
-
-    dest->setPC(src->readPC());
-    dest->setNextPC(src->readNextPC());
-}
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/registers.hh
index fd9d6d546..e221c4a81 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/registers.hh
@@ -55,40 +55,78 @@
  * Authors: Gabe Black
  */
 
-#ifndef __ARCH_X86_REGFILE_HH__
-#define __ARCH_X86_REGFILE_HH__
-
-#include <iostream>
-#include <string>
+#ifndef __ARCH_X86_REGISTERS_HH__
+#define __ARCH_X86_REGISTERS_HH__
 
 #include "arch/x86/intregs.hh"
+#include "arch/x86/max_inst_regs.hh"
 #include "arch/x86/miscregs.hh"
 #include "arch/x86/x86_traits.hh"
 
-class Checkpoint;
-class EventManager;
-class ThreadContext;
-
 namespace X86ISA
 {
-    const int NumMiscArchRegs = NUM_MISCREGS;
-    const int NumMiscRegs = NUM_MISCREGS;
+using X86ISAInst::MaxInstSrcRegs;
+using X86ISAInst::MaxInstDestRegs;
+const int NumMiscArchRegs = NUM_MISCREGS;
+const int NumMiscRegs = NUM_MISCREGS;
+
+const int NumIntArchRegs = NUM_INTREGS;
+const int NumIntRegs =
+    NumIntArchRegs + NumMicroIntRegs +
+    NumPseudoIntRegs + NumImplicitIntRegs;
 
-    const int NumIntArchRegs = NUM_INTREGS;
-    const int NumIntRegs =
-        NumIntArchRegs + NumMicroIntRegs +
-        NumPseudoIntRegs + NumImplicitIntRegs;
+//Each 128 bit xmm register is broken into two effective 64 bit registers.
+const int NumFloatRegs =
+    NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
+const int NumFloatArchRegs = NumFloatRegs + 8;
 
-    //Each 128 bit xmm register is broken into two effective 64 bit registers.
-    const int NumFloatRegs =
-        NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
-    const int NumFloatArchRegs = NumFloatRegs + 8;
+// These enumerate all the registers for dependence tracking.
+enum DependenceTags {
+    //There are 16 microcode registers at the moment. This is an
+    //unusually large constant to make sure there isn't overflow.
+    FP_Base_DepTag = 128,
+    Ctrl_Base_DepTag =
+        FP_Base_DepTag +
+        //mmx/x87 registers
+        8 +
+        //xmm registers
+        16 * 2 +
+        //The microcode fp registers
+        8 +
+        //The indices that are mapped over the fp stack
+        8
+};
 
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
+// semantically meaningful register indices
+//There is no such register in X86
+const int ZeroReg = NUM_INTREGS;
+const int StackPointerReg = INTREG_RSP;
+//X86 doesn't seem to have a link register
+const int ReturnAddressReg = 0;
+const int ReturnValueReg = INTREG_RAX;
+const int FramePointerReg = INTREG_RBP;
 
-    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+// Some OS syscalls use a second register (rdx) to return a second
+// value
+const int SyscallPseudoReturnReg = INTREG_RDX;
+
+typedef uint64_t IntReg;
+//XXX Should this be a 128 bit structure for XMM memory ops?
+typedef uint64_t LargestRead;
+typedef uint64_t MiscReg;
+
+//These floating point types are correct for mmx, but not
+//technically for x87 (80 bits) or at all for xmm (128 bits)
+typedef double FloatReg;
+typedef uint64_t FloatRegBits;
+typedef union
+{
+    IntReg intReg;
+    FloatReg fpReg;
+    MiscReg ctrlReg;
+} AnyReg;
 
-    int InterruptLevel(uint64_t softint);
+typedef uint16_t RegIndex;
 
 }; // namespace X86ISA
 
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index c06d664eb..bdf3a814e 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -230,24 +230,6 @@ namespace X86ISA
         return true;
     }
 
-    typedef uint64_t IntReg;
-    //XXX Should this be a 128 bit structure for XMM memory ops?
-    typedef uint64_t LargestRead;
-    typedef uint64_t MiscReg;
-
-    //These floating point types are correct for mmx, but not
-    //technically for x87 (80 bits) or at all for xmm (128 bits)
-    typedef double FloatReg;
-    typedef uint64_t FloatRegBits;
-    typedef union
-    {
-        IntReg intReg;
-        FloatReg fpReg;
-        MiscReg ctrlReg;
-    } AnyReg;
-
-    typedef uint16_t RegIndex;
-
     struct CoreSpecific {
         int core_type;
     };
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 9e96b654d..802328db1 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -225,4 +225,30 @@ void startupCPU(ThreadContext *tc, int cpuId)
 #endif
 }
 
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    warn("copyMiscRegs is naively implemented for x86\n");
+    for (int i = 0; i < NUM_MISCREGS; ++i) {
+        if ( ( i != MISCREG_CR1 &&
+             !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
+             !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
+             continue;
+        }
+        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
+    }
+}
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("copyRegs not implemented for x86!\n");
+    //copy int regs
+    //copy float regs
+    copyMiscRegs(src, dest);
+
+    dest->setPC(src->readPC());
+    dest->setNextPC(src->readNextPC());
+}
+
 } //namespace X86_ISA
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index dbb2bc361..d305e2599 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -154,6 +154,10 @@ namespace X86ISA
 #endif
 
     void startupCPU(ThreadContext *tc, int cpuId);
+
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 };
 
 #endif // __ARCH_X86_UTILITY_HH__