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authorAli Saidi <saidi@eecs.umich.edu>2008-10-20 16:22:59 -0400
committerAli Saidi <saidi@eecs.umich.edu>2008-10-20 16:22:59 -0400
commitb760b99f4d9f5469d88c67ae8a06e5f9543a43e7 (patch)
tree39cb41ec58be172c0f4b65162ae637be42bbabb0 /src/arch/x86
parent4fac54f227f0ee0ee169955cb2510609434f7d85 (diff)
downloadgem5-b760b99f4d9f5469d88c67ae8a06e5f9543a43e7.tar.xz
O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change.
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/bios/IntelMP.py9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/arch/x86/bios/IntelMP.py b/src/arch/x86/bios/IntelMP.py
index 758932180..70e7963fa 100644
--- a/src/arch/x86/bios/IntelMP.py
+++ b/src/arch/x86/bios/IntelMP.py
@@ -86,15 +86,6 @@ class X86IntelMPConfigTable(SimObject):
ext_entries = VectorParam.X86IntelMPExtConfigEntry([],
'extended configuration table entries')
- def add_entry(self, entry):
- if isinstance(entry, X86IntelMPBaseConfigEntry):
- self.base_entries.append(entry)
- elif isinstance(entry, X86IntelMPExtConfigEntry):
- self.base_entries.append(entry)
- else:
- panic("Don't know what type of Intel MP entry %s is." \
- % entry.__class__.__name__)
-
class X86IntelMPBaseConfigEntry(SimObject):
type = 'X86IntelMPBaseConfigEntry'
cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'