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authorTushar Krishna <Tushar.Krishna@amd.com>2010-07-21 09:55:57 -0700
committerTushar Krishna <Tushar.Krishna@amd.com>2010-07-21 09:55:57 -0700
commit11bb678a8017bba31c69847ee87212579b6b2f02 (patch)
treeeaec635f4934676093610046e1e776f2d3e6bf83 /src/arch/x86
parent262b2e2b942f15384393b421ece5bb9a2ac48ee1 (diff)
downloadgem5-11bb678a8017bba31c69847ee87212579b6b2f02.tar.xz
Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
index 03752c28a..6504b5ab4 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
@@ -50,31 +50,31 @@ def macroop XCHG_R_R
def macroop XCHG_R_M
{
- ldst t1, seg, sib, disp
- st reg, seg, sib, disp
+ ldstl t1, seg, sib, disp
+ stul reg, seg, sib, disp
mov reg, reg, t1
};
def macroop XCHG_R_P
{
rdip t7
- ldst t1, seg, riprel, disp
- st reg, seg, riprel, disp
+ ldstl t1, seg, riprel, disp
+ stul reg, seg, riprel, disp
mov reg, reg, t1
};
def macroop XCHG_M_R
{
- ldst t1, seg, sib, disp
- st reg, seg, sib, disp
+ ldstl t1, seg, sib, disp
+ stul reg, seg, sib, disp
mov reg, reg, t1
};
def macroop XCHG_P_R
{
rdip t7
- ldst t1, seg, riprel, disp
- st reg, seg, riprel, disp
+ ldstl t1, seg, riprel, disp
+ stul reg, seg, riprel, disp
mov reg, reg, t1
};