summaryrefslogtreecommitdiff
path: root/src/arch/x86
diff options
context:
space:
mode:
authorAlexandru Dutu <alexandru.dutu@amd.com>2014-11-23 18:01:09 -0800
committerAlexandru Dutu <alexandru.dutu@amd.com>2014-11-23 18:01:09 -0800
commit1f539f13c32ad5a9187d56a098d4c857639b0e05 (patch)
tree7618c3b946d9c25d9b22018f226eee77b6de4aaf /src/arch/x86
parentc11bcb8119273ef91c40a25b8fd9471a887d0ee5 (diff)
downloadgem5-1f539f13c32ad5a9187d56a098d4c857639b0e05.tar.xz
mem: Page Table map api modification
This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes.
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/pagetable.cc8
-rw-r--r--src/arch/x86/pagetable.hh36
2 files changed, 27 insertions, 17 deletions
diff --git a/src/arch/x86/pagetable.cc b/src/arch/x86/pagetable.cc
index a9ef18129..cd4df42e7 100644
--- a/src/arch/x86/pagetable.cc
+++ b/src/arch/x86/pagetable.cc
@@ -45,9 +45,11 @@
namespace X86ISA
{
-TlbEntry::TlbEntry(Addr asn, Addr _vaddr, Addr _paddr) :
- paddr(_paddr), vaddr(_vaddr), logBytes(PageShift), writable(true),
- user(true), uncacheable(false), global(false), patBit(0), noExec(false)
+TlbEntry::TlbEntry(Addr asn, Addr _vaddr, Addr _paddr,
+ bool uncacheable, bool read_only) :
+ paddr(_paddr), vaddr(_vaddr), logBytes(PageShift), writable(!read_only),
+ user(true), uncacheable(uncacheable), global(false), patBit(0),
+ noExec(false)
{}
void
diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index 86e488bdc..639815893 100644
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -128,7 +128,8 @@ namespace X86ISA
TlbEntryTrie::Handle trieHandle;
- TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
+ TlbEntry(Addr asn, Addr _vaddr, Addr _paddr,
+ bool uncacheable, bool read_only);
TlbEntry() {}
void
@@ -157,13 +158,12 @@ namespace X86ISA
*/
const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9};
+ /* x86 specific PTE flags */
enum PTEField{
- PTE_NotPresent = 0,
- PTE_Present,
- PTE_ReadOnly = 0,
- PTE_ReadWrite,
- PTE_Supervisor = 0,
- PTE_UserSupervisor,
+ PTE_NotPresent = 1,
+ PTE_Supervisor = 2,
+ PTE_ReadOnly = 4,
+ PTE_Uncacheable = 8,
};
/** Page table operations specific to x86 ISA.
@@ -172,14 +172,12 @@ namespace X86ISA
class PageTableOps
{
public:
- void setPTEFields(PageTableEntry& PTE,
- uint64_t present = PTE_Present,
- uint64_t read_write = PTE_ReadWrite,
- uint64_t user_supervisor = PTE_UserSupervisor)
+ void setPTEFields(PageTableEntry& PTE, uint64_t flags = 0)
{
- PTE.p = present;
- PTE.w = read_write;
- PTE.u = user_supervisor;// both user and supervisor access allowed
+ PTE.p = flags & PTE_NotPresent ? 0 : 1;
+ PTE.pcd = flags & PTE_Uncacheable ? 1 : 0;
+ PTE.w = flags & PTE_ReadOnly ? 0 : 1;
+ PTE.u = flags & PTE_Supervisor ? 0 : 1;
}
/** returns the physical memory address of the page table */
@@ -196,6 +194,16 @@ namespace X86ISA
return PTE.base;
}
+ bool isUncacheable(const PageTableEntry PTE)
+ {
+ return PTE.pcd;
+ }
+
+ bool isReadOnly(PageTableEntry PTE)
+ {
+ return !PTE.w;
+ }
+
/** sets the page number in a page table entry */
void setPnum(PageTableEntry& PTE, Addr paddr)
{