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authorGabe Black <gabeblack@google.com>2018-01-08 23:37:57 -0800
committerGabe Black <gabeblack@google.com>2018-01-23 20:39:17 +0000
commita4e722725c90677d555675eca616c9d0990393f1 (patch)
treeed9a8268f73742fd4b4acbaf8e8434b67dc5fed7 /src/arch/x86
parentdb8c55dede65e07cb9ea8e95c48badd2ea24462f (diff)
downloadgem5-a4e722725c90677d555675eca616c9d0990393f1.tar.xz
tarch, mem: Abstract the data stored in the SE page tables.
Rather than store the actual TLB entry that corresponds to a mapping, we can just store some abstracted information (address, a few flags) and then let the caller turn that into the appropriate entry. There could potentially be some small amount of overhead from creating entries vs. storing them and just installing them, but it's likely pretty minimal since that only happens on a TLB miss (ideally rare), and, if it is problematic, there could be some preallocated TLB entries which are just minimally filled in as necessary. This has the nice effect of finally making the page tables ISA agnostic. Change-Id: I11e630f60682f0a0029b0683eb8ff0135fbd4317 Reviewed-on: https://gem5-review.googlesource.com/7350 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/tlb.cc16
1 files changed, 10 insertions, 6 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 93369494d..a3aec1676 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -357,22 +357,26 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
assert(entry);
} else {
Process *p = tc->getProcessPtr();
- TlbEntry *newEntry = p->pTable->lookup(vaddr);
- if (!newEntry && mode != Execute) {
+ const EmulationPageTable::Entry *pte =
+ p->pTable->lookup(vaddr);
+ if (!pte && mode != Execute) {
// Check if we just need to grow the stack.
if (p->fixupStackFault(vaddr)) {
// If we did, lookup the entry for the new page.
- newEntry = p->pTable->lookup(vaddr);
+ pte = p->pTable->lookup(vaddr);
}
}
- if (!newEntry) {
+ if (!pte) {
return std::make_shared<PageFault>(vaddr, true, mode,
true, false);
} else {
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
- newEntry->pageStart());
- entry = insert(alignedVaddr, *newEntry);
+ pte->paddr);
+ entry = insert(alignedVaddr, TlbEntry(
+ p->pTable->pid(), alignedVaddr, pte->paddr,
+ pte->flags & EmulationPageTable::Uncacheable,
+ pte->flags & EmulationPageTable::ReadOnly));
}
DPRINTF(TLB, "Miss was serviced.\n");
}