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authorGabe Black <gblack@eecs.umich.edu>2009-02-27 09:26:26 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-27 09:26:26 -0800
commitb36f28472d4e28263f4d2e3f6b3e88c9fa350ca1 (patch)
tree3acfcc51356c66e4c95f3b1c307d37d466eb8a04 /src/arch/x86
parent2fe87e62ba2bf51dfc773dd6fdb2bd1fdb09e20b (diff)
downloadgem5-b36f28472d4e28263f4d2e3f6b3e88c9fa350ca1.tar.xz
X86: Implement shrd.
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py35
2 files changed, 36 insertions, 1 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index c3fb5c19d..1ee62142a 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -830,7 +830,7 @@
0x1: pop_gs();
0x2: rsm_smm();
0x3: Inst::BTS(Ev,Gv);
- 0x4: shrd_Ev_Gv_Ib();
+ 0x4: Inst::SHRD(Ev,Gv,Ib);
0x5: shrd_Ev_Gv_rCl();
//0x6: group16();
0x6: decode MODRM_REG {
diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
index 138082eb2..caaeca974 100644
--- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
@@ -174,6 +174,41 @@ def macroop SHR_P_R
st t1, seg, riprel, disp
};
+# SHRD will not set OF correctly when the shift count is 1.
+def macroop SHRD_R_R_I
+{
+ srli t1, reg, imm, flags=(CF,)
+ rori t2, regm, imm
+ srli t3, regm, imm
+ xor t2, t2, t3
+ or reg, t1, t2
+};
+
+# SHRD will not set OF correctly when the shift count is 1.
+def macroop SHRD_M_R_I
+{
+ ldst t1, seg, sib, disp
+ srli t1, t1, imm, flags=(CF,)
+ rori t2, reg, imm
+ srli t3, reg, imm
+ xor t2, t2, t3
+ or t1, t1, t2
+ st t1, seg, sib, disp
+};
+
+# SHRD will not set OF correctly when the shift count is 1.
+def macroop SHRD_P_R_I
+{
+ rdip t7
+ ldst t1, seg, riprel, disp
+ srli t1, t1, imm, flags=(CF,)
+ rori t2, reg, imm
+ srli t3, reg, imm
+ xor t2, t2, t3
+ or t1, t1, t2
+ st t1, seg, riprel, disp
+};
+
def macroop SAR_R_I
{
srai reg, reg, imm, flags=(CF,OF,SF,ZF,PF)