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authorAndreas Sandberg <andreas@sandberg.pp.se>2013-09-30 12:20:43 +0200
committerAndreas Sandberg <andreas@sandberg.pp.se>2013-09-30 12:20:43 +0200
commitd9856f33a455b9c86b90f5857df866fba3aa5bfb (patch)
tree289321ea932492066e8579e101ea116cc9fd1b0c /src/arch/x86
parent114b643dd0125518c5f0b40959057dcf316f5007 (diff)
downloadgem5-d9856f33a455b9c86b90f5857df866fba3aa5bfb.tar.xz
arch: Add support for m5ops using mmapped IPRs
In order to support m5ops on virtualized CPUs, we need to either intercept hypercall instructions or provide a memory mapped m5ops interface. Since KVM does not normally pass the results of hypercalls to userspace, which makes that method unfeasible. This changeset introduces support for m5ops using memory mapped mmapped IPRs. This is implemented by adding a class of "generic" IPRs which are handled by architecture-independent code. Such IPRs always have bit 63 set and are handled by handleGenericIprRead() and handleGenericIprWrite(). Platform specific impementations of handleIprRead and handleIprWrite should use GenericISA::isGenericIprAccess to determine if an IPR address should be handled by the generic code instead of the architecture-specific code. Platforms that don't need their own IPR support can reuse GenericISA::handleIprRead() and GenericISA::handleIprWrite().
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/mmapped_ipr.hh43
1 files changed, 27 insertions, 16 deletions
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index 02c125171..bd24d33da 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -46,6 +46,7 @@
* ISA-specific helper functions for memory mapped IPR accesses.
*/
+#include "arch/generic/mmapped_ipr.hh"
#include "arch/x86/regs/misc.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
@@ -56,27 +57,37 @@ namespace X86ISA
inline Cycles
handleIprRead(ThreadContext *xc, Packet *pkt)
{
- Addr offset = pkt->getAddr() & mask(3);
- MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
- MiscReg data = htog(xc->readMiscReg(index));
- // Make sure we don't trot off the end of data.
- assert(offset + pkt->getSize() <= sizeof(MiscReg));
- pkt->setData(((uint8_t *)&data) + offset);
- return Cycles(1);
+ if (GenericISA::isGenericIprAccess(pkt)) {
+ return GenericISA::handleGenericIprRead(xc, pkt);
+ } else {
+ Addr offset = pkt->getAddr() & mask(3);
+ MiscRegIndex index = (MiscRegIndex)(
+ pkt->getAddr() / sizeof(MiscReg));
+ MiscReg data = htog(xc->readMiscReg(index));
+ // Make sure we don't trot off the end of data.
+ assert(offset + pkt->getSize() <= sizeof(MiscReg));
+ pkt->setData(((uint8_t *)&data) + offset);
+ return Cycles(1);
+ }
}
inline Cycles
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
- Addr offset = pkt->getAddr() & mask(3);
- MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
- MiscReg data;
- data = htog(xc->readMiscRegNoEffect(index));
- // Make sure we don't trot off the end of data.
- assert(offset + pkt->getSize() <= sizeof(MiscReg));
- pkt->writeData(((uint8_t *)&data) + offset);
- xc->setMiscReg(index, gtoh(data));
- return Cycles(1);
+ if (GenericISA::isGenericIprAccess(pkt)) {
+ return GenericISA::handleGenericIprWrite(xc, pkt);
+ } else {
+ Addr offset = pkt->getAddr() & mask(3);
+ MiscRegIndex index = (MiscRegIndex)(
+ pkt->getAddr() / sizeof(MiscReg));
+ MiscReg data;
+ data = htog(xc->readMiscRegNoEffect(index));
+ // Make sure we don't trot off the end of data.
+ assert(offset + pkt->getSize() <= sizeof(MiscReg));
+ pkt->writeData(((uint8_t *)&data) + offset);
+ xc->setMiscReg(index, gtoh(data));
+ return Cycles(1);
+ }
}
}