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authorTimothy M. Jones <tjones1@inf.ed.ac.uk>2010-02-12 19:53:20 +0000
committerTimothy M. Jones <tjones1@inf.ed.ac.uk>2010-02-12 19:53:20 +0000
commit29e8bcead5700f638c4848d9b5710d0ebf18d64b (patch)
treee85dac6557f13146ae2cb119d3ea5b515f3f9e29 /src/arch/x86
parent7fe9f92cfc73147a1a024c1632c9a7619c1779d1 (diff)
downloadgem5-29e8bcead5700f638c4848d9b5710d0ebf18d64b.tar.xz
O3PCU: Split loads and stores that cross cache line boundaries.
When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them.
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/isa_traits.hh3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 9f1b7b7c4..80af12c91 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -91,6 +91,9 @@ namespace X86ISA
StaticInstPtr decodeInst(ExtMachInst);
const Addr LoadAddrMask = ULL(-1);
+
+ // Memory accesses can be unaligned
+ const bool HasUnalignedMemAcc = true;
};
#endif // __ARCH_X86_ISATRAITS_HH__