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authorGeoffrey Blake <geoffrey.blake@arm.com>2012-03-09 09:59:28 -0500
committerGeoffrey Blake <geoffrey.blake@arm.com>2012-03-09 09:59:28 -0500
commit98cf57fb89b76a8ca423083d52cc647c7923fe51 (patch)
tree0376266c9e2b9381354bf86b3c7f2db4981577ea /src/arch/x86
parent043709fdfab3b6c46f6ef95d1f642cd3c06ee20a (diff)
downloadgem5-98cf57fb89b76a8ca423083d52cc647c7923fe51.tar.xz
CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible with ISAs other than ARM. This patch adds the appropriate function stubs to allow compilation.
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/tlb.cc7
-rw-r--r--src/arch/x86/tlb.hh4
2 files changed, 11 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 456f03208..b7d0b828c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -405,6 +405,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(fault, req, tc, mode);
}
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+ panic("Not implemented\n");
+ return NoFault;
+}
+
Walker *
TLB::getWalker()
{
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index a943683af..078b8b8d6 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -114,6 +114,10 @@ namespace X86ISA
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
+ /** Stub function for compilation support of CheckerCPU. x86 ISA does
+ * not support Checker model at the moment
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
TlbEntry * insert(Addr vpn, TlbEntry &entry);