arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.

4 files changed, 70 insertions, 5 deletions

diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 92b30ced1..6ec714e8e 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -73,6 +73,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('utility.cc')
     Source('vtophys.cc')
 
+    SimObject('X86ISA.py')
     SimObject('X86LocalApic.py')
     SimObject('X86NativeTrace.py')
     SimObject('X86System.py')
diff --git a/src/arch/x86/X86ISA.py b/src/arch/x86/X86ISA.py
new file mode 100644
index 000000000..75d8e85c9
--- /dev/null
+++ b/src/arch/x86/X86ISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class X86ISA(SimObject):
+    type = 'X86ISA'
+    cxx_class = 'X86ISA::ISA'
+    cxx_header = "arch/x86/isa.hh"
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 1a9b39840..9dbab8c7e 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -33,6 +33,7 @@
 #include "arch/x86/tlb.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "params/X86ISA.hh"
 #include "sim/serialize.hh"
 
 namespace X86ISA
@@ -110,6 +111,18 @@ ISA::clear()
     regVal[MISCREG_DR7] = 1 << 10;
 }
 
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    clear();
+}
+
+const X86ISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 MiscReg
 ISA::readMiscRegNoEffect(int miscReg)
 {
@@ -376,3 +389,9 @@ ISA::unserialize(EventManager *em, Checkpoint * cp,
 }
 
 }
+
+X86ISA::ISA *
+X86ISAParams::create()
+{
+    return new X86ISA::ISA(this);
+}
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 7b0c7b61a..39ed68ea5 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -38,14 +38,16 @@
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/registers.hh"
 #include "base/types.hh"
+#include "sim/sim_object.hh"
 
 class Checkpoint;
 class EventManager;
 class ThreadContext;
+struct X86ISAParams;
 
 namespace X86ISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       protected:
         MiscReg regVal[NUM_MISCREGS];
@@ -54,12 +56,12 @@ namespace X86ISA
                 ThreadContext *tc);
 
       public:
+        typedef X86ISAParams Params;
+
         void clear();
 
-        ISA()
-        {
-            clear();
-        }
+        ISA(Params *p);
+        const Params *params() const;
 
         MiscReg readMiscRegNoEffect(int miscReg);
         MiscReg readMiscReg(int miscReg, ThreadContext *tc);