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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2015-02-11 10:23:27 -0500
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2015-02-11 10:23:27 -0500
commit550c31849024a2184887df87aae39617ebfe0d6a (patch)
tree53cc5e91d0961b0215c614141fdc380b30c76951 /src/arch/x86
parent9e6f803254cbf3f5f491775debdc6593c3329da8 (diff)
downloadgem5-550c31849024a2184887df87aae39617ebfe0d6a.tar.xz
sim: Move the BaseTLB to src/arch/generic/
The TLB-related code is generally architecture dependent and should live in the arch directory to signify that. --HG-- rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py rename : src/sim/tlb.cc => src/arch/generic/tlb.cc rename : src/sim/tlb.hh => src/arch/generic/tlb.hh
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/faults.hh2
-rw-r--r--src/arch/x86/tlb.hh2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index b43cda36a..b9eb85e21 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -42,10 +42,10 @@
#include <string>
+#include "arch/generic/tlb.hh"
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "sim/faults.hh"
-#include "sim/tlb.hh"
namespace X86ISA
{
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index e1089f90c..77f9fc49d 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -44,6 +44,7 @@
#include <string>
#include <vector>
+#include "arch/generic/tlb.hh"
#include "arch/x86/regs/segment.hh"
#include "arch/x86/pagetable.hh"
#include "base/trie.hh"
@@ -51,7 +52,6 @@
#include "mem/request.hh"
#include "params/X86TLB.hh"
#include "sim/sim_object.hh"
-#include "sim/tlb.hh"
class ThreadContext;
class Packet;