X86: Implement the xadd instruction.

2 files changed, 24 insertions, 4 deletions

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 064f5ce86..3cdfa48bb 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -870,8 +870,8 @@
                 0x7: Inst::MOVSX_W(Gv,Ev);
             }
             0x18: decode OPCODE_OP_BOTTOM3 {
-                0x0: xadd_Eb_Gb();
-                0x1: xadd_Ev_Gv();
+                0x0: Inst::XADD(Eb,Gb);
+                0x1: Inst::XADD(Ev,Gv);
                 //0x7: group9();
                 0x7: decode MODRM_REG {
                     0x1: cmpxchg_Mq();
diff --git a/src/arch/x86/isa/insts/general_purpose/semaphores.py b/src/arch/x86/isa/insts/general_purpose/semaphores.py
index da16477fc..f23241863 100644
--- a/src/arch/x86/isa/insts/general_purpose/semaphores.py
+++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py
@@ -78,10 +78,30 @@ def macroop CMPXCHG_P_R {
     st t1, seg, riprel, disp
     mov rax, rax, t1, flags=(nCZF,)
 };
+
+def macroop XADD_M_R {
+    ldst t1, seg, sib, disp
+    add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
+    st t2, seg, sib, disp
+    mov reg, reg, t1
+};
+
+def macroop XADD_P_R {
+    rdip t7
+    ldst t1, seg, riprel, disp
+    add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
+    st t2, seg, riprel, disp
+    mov reg, reg, t1
+};
+
+def macroop XADD_R_R {
+    add t2, regm, reg, flags=(OF,SF,ZF,AF,PF,CF)
+    mov regm, regm, reg
+    mov reg, reg, t2
+};
+
 '''
 #let {{
-#    class XADD(Inst):
-#       "GenFault ${new UnimpInstFault}"
 #    class XCHG(Inst):
 #       "GenFault ${new UnimpInstFault}"
 #}};