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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-03-01 22:42:18 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-03-01 22:42:18 -0800 |
| commit | 72d35701e9842a454ea0bd1e4546d161c3024f93 (patch) | |
| tree | e24e0f4e99c8fae4dd6d964a157ac0392f0aefba /src/arch/x86 | |
| parent | 3a10b200f7d663ebc1fecc7449871a2cd356e815 (diff) | |
| download | gem5-72d35701e9842a454ea0bd1e4546d161c3024f93.tar.xz | |
X86: Mark prefetches as such in their instruction and request flags.
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/isa/microops/ldstop.isa | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index cd649d644..86c2dccf7 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -282,8 +282,10 @@ let {{ self.memFlags = baseFlags if atCPL0: self.memFlags += " | (CPL0FlagBit << FlagShift)" + self.instFlags = "" if prefetch: self.memFlags += " | Request::PREFETCH" + self.instFlags += " | StaticInst::IsDataPrefetch" self.memFlags += " | (machInst.legacy.addr ? " + \ "(AddrSizeFlagBit << FlagShift) : 0)" @@ -293,7 +295,7 @@ let {{ %(disp)s, %(segment)s, %(data)s, %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { "class_name" : self.className, - "flags" : self.microFlagsText(microFlags), + "flags" : self.microFlagsText(microFlags) + self.instFlags, "scale" : self.scale, "index" : self.index, "base" : self.base, "disp" : self.disp, |