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author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-19 18:26:42 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-19 18:26:42 -0700 |
commit | f3f3747431e001dc6c80da5b6489516b610c22d6 (patch) | |
tree | 24fcbc928df1619a82dbfd9ffa6d6f6809f509f6 /src/arch/x86 | |
parent | a54ae9f92b6000e8aaf5e056deaead8725c25a74 (diff) | |
download | gem5-f3f3747431e001dc6c80da5b6489516b610c22d6.tar.xz |
X86: Put in the foundation for x87 stack based fp registers.
--HG--
extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
Diffstat (limited to 'src/arch/x86')
-rw-r--r-- | src/arch/x86/floatregfile.hh | 5 | ||||
-rw-r--r-- | src/arch/x86/floatregs.hh | 6 | ||||
-rw-r--r-- | src/arch/x86/isa/microasm.isa | 5 | ||||
-rw-r--r-- | src/arch/x86/isa/operands.isa | 3 | ||||
-rw-r--r-- | src/arch/x86/isa_traits.hh | 4 | ||||
-rw-r--r-- | src/arch/x86/miscregs.hh | 5 | ||||
-rw-r--r-- | src/arch/x86/regfile.cc | 10 | ||||
-rw-r--r-- | src/arch/x86/regfile.hh | 2 |
8 files changed, 36 insertions, 4 deletions
diff --git a/src/arch/x86/floatregfile.hh b/src/arch/x86/floatregfile.hh index 14dda443f..b77ddb0eb 100644 --- a/src/arch/x86/floatregfile.hh +++ b/src/arch/x86/floatregfile.hh @@ -101,8 +101,9 @@ namespace X86ISA std::string getFloatRegName(RegIndex); //Each 128 bit xmm register is broken into two effective 64 bit registers. - const int NumFloatArchRegs = NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; - const int NumFloatRegs = NumFloatArchRegs; + const int NumFloatRegs = + NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; + const int NumFloatArchRegs = NumFloatRegs + 8; class FloatRegFile { diff --git a/src/arch/x86/floatregs.hh b/src/arch/x86/floatregs.hh index b9d6a5c43..30846ec00 100644 --- a/src/arch/x86/floatregs.hh +++ b/src/arch/x86/floatregs.hh @@ -162,6 +162,12 @@ namespace X86ISA { return (FloatRegIndex)(FLOATREG_MICROFP_BASE + index); } + + static inline FloatRegIndex + FLOATREG_STACK(int index, int top) + { + return (FloatRegIndex)(NUM_FLOATREGS + ((top - index + 8) % 8)); + } }; #endif // __ARCH_X86_FLOATREGS_HH__ diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 579909506..e961cc63c 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -136,5 +136,10 @@ let {{ assembler.symbols["label"] = labeler + def stack_index(index): + return "(NUM_FLOATREGS + (%s))" % index + + assembler.symbols["st"] = stack_index + macroopDict = assembler.assemble(microcode) }}; diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 7b0427b44..05a9f4418 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -115,6 +115,9 @@ def operands {{ 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60), + # The TOP register should needs to be more protected so that later + # instructions don't map their indexes with an old value. + 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61), 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index 602c99390..f3478d7f6 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -89,7 +89,9 @@ namespace X86ISA //mmx/x87 registers 8 + //xmm registers - 16 + 16 + + //The indices that are mapped over the fp stack + 8 }; // semantically meaningful register indices diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh index 01499e7ad..bab813719 100644 --- a/src/arch/x86/miscregs.hh +++ b/src/arch/x86/miscregs.hh @@ -171,9 +171,12 @@ namespace X86ISA MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE, MISCREG_TR_ATTR, + // Floating point control registers + MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments, + //XXX Add "Model-Specific Registers" - NUM_MISCREGS = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments + NUM_MISCREGS }; static inline MiscRegIndex diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc index 96283cada..889f2f5cd 100644 --- a/src/arch/x86/regfile.cc +++ b/src/arch/x86/regfile.cc @@ -85,6 +85,7 @@ * Authors: Gabe Black */ +#include "arch/x86/floatregs.hh" #include "arch/x86/regfile.hh" #include "base/trace.hh" #include "sim/serialize.hh" @@ -218,6 +219,15 @@ int X86ISA::flattenIntIndex(ThreadContext * tc, int reg) return (reg & ~(1 << 6)); } +int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg) +{ + if (reg > NUM_FLOATREGS) { + int top = tc->readMiscRegNoEffect(MISCREG_X87_TOP); + reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top); + } + return reg; +} + void RegFile::serialize(std::ostream &os) { intRegFile.serialize(os); diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh index d4425b04c..650181aca 100644 --- a/src/arch/x86/regfile.hh +++ b/src/arch/x86/regfile.hh @@ -149,6 +149,8 @@ namespace X86ISA int flattenIntIndex(ThreadContext * tc, int reg); + int flattenFloatIndex(ThreadContext * tc, int reg); + void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); |