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authorNilay Vaish <nilay@cs.wisc.edu>2015-07-28 01:58:04 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-07-28 01:58:04 -0500
commitaafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch)
treed40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/arch/x86
parent608641e23c7f2288810c3f23a1a63790b664f2ab (diff)
downloadgem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz
revert 5af8f40d8f2c
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/insts/static_inst.cc7
-rw-r--r--src/arch/x86/isa.hh6
-rw-r--r--src/arch/x86/registers.hh11
-rw-r--r--src/arch/x86/utility.cc4
4 files changed, 1 insertions, 27 deletions
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index 49ea6ef4e..39091289f 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -225,19 +225,12 @@ namespace X86ISA
ccprintf(os, "%%cc%d", rel_reg);
break;
- case VectorRegClass:
- ccprintf(os, "%%cc%d", rel_reg);
- break;
-
case MiscRegClass:
switch (rel_reg) {
default:
ccprintf(os, "%%ctrl%d", rel_reg);
}
break;
-
- default:
- panic("Invalid register class!\n");
}
}
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 779241c55..88f4980ae 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -92,12 +92,6 @@ namespace X86ISA
}
int
- flattenVectorIndex(int reg) const
- {
- return reg;
- }
-
- int
flattenMiscIndex(int reg) const
{
return reg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index ad40fe17f..ebd88136e 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -57,7 +57,6 @@ const int NumMiscRegs = NUM_MISCREGS;
const int NumIntArchRegs = NUM_INTREGS;
const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
const int NumCCRegs = NUM_CCREGS;
-const int NumVectorRegs = 0;
#define ISA_HAS_CC_REGS
@@ -73,8 +72,7 @@ enum DependenceTags {
// we just start at (1 << 7) == 128.
FP_Reg_Base = 128,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
- Vector_Reg_Base = CC_Reg_Base + NumCCRegs,
- Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs,
+ Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
};
@@ -93,13 +91,6 @@ const int SyscallPseudoReturnReg = INTREG_RDX;
typedef uint64_t IntReg;
typedef uint64_t CCReg;
-
-// vector register file entry type
-typedef uint64_t VectorRegElement;
-const int NumVectorRegElements = 0;
-const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
-typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
-
//XXX Should this be a 128 bit structure for XMM memory ops?
typedef uint64_t LargestRead;
typedef uint64_t MiscReg;
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index e1be61180..f7d0f816e 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -245,10 +245,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
//copy condition-code regs
for (int i = 0; i < NumCCRegs; ++i)
dest->setCCRegFlat(i, src->readCCRegFlat(i));
-
- // copy vector regs when added to the architecture
- assert(NumVectorRegs == 0);
-
copyMiscRegs(src, dest);
dest->pcState(src->pcState());
}