kvm, x86: Adding support for SE mode execution

This patch adds methods in KvmCPU model to handle KVM exits caused by syscall
instructions and page faults. These types of exits will be encountered if
KvmCPU is run in SE mode.

5 files changed, 123 insertions, 12 deletions

diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 1c8277482..bdc012259 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -64,6 +64,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('pagetable.cc')
     Source('pagetable_walker.cc')
     Source('process.cc')
+    Source('pseudo_inst.cc')
     Source('remote_gdb.cc')
     Source('stacktrace.cc')
     Source('system.cc')
diff --git a/src/arch/x86/pseudo_inst.cc b/src/arch/x86/pseudo_inst.cc
new file mode 100644
index 000000000..bd3b5ac7c
--- /dev/null
+++ b/src/arch/x86/pseudo_inst.cc
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+#include "arch/x86/pseudo_inst.hh"
+#include "debug/PseudoInst.hh"
+#include "sim/process.hh"
+
+using namespace X86ISA;
+
+namespace X86ISA {
+
+/*
+ * This function is executed when the simulation is executing the syscall
+ * handler in System Emulation mode.
+ */
+void
+m5Syscall(ThreadContext *tc)
+{
+    DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n");
+
+    tc->syscall(tc->readIntReg(INTREG_RAX));
+    MiscReg rflags = tc->readMiscReg(MISCREG_RFLAGS);
+    rflags &= ~(1 << 16);
+    tc->setMiscReg(MISCREG_RFLAGS, rflags);
+}
+
+/*
+ * This function is executed when the simulation is executing the pagefault
+ * handler in System Emulation mode.
+ */
+void
+m5PageFault(ThreadContext *tc)
+{
+    DPRINTF(PseudoInst, "PseudoInst::m5PageFault()\n");
+
+    Process *p = tc->getProcessPtr();
+    if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) {
+        panic("Page fault at %#x ", tc->readMiscReg(MISCREG_CR2));
+    }
+}
+
+} // namespace X86ISA
diff --git a/src/arch/x86/pseudo_inst.hh b/src/arch/x86/pseudo_inst.hh
new file mode 100644
index 000000000..5074d1fc3
--- /dev/null
+++ b/src/arch/x86/pseudo_inst.hh
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+#ifndef __ARCH_X86_PSEUDO_INST_HH__
+#define __ARCH_X86_PSEUDO_INST_HH__
+
+class ThreadContext;
+
+namespace X86ISA {
+    void m5Syscall(ThreadContext *tc);
+    void m5PageFault(ThreadContext *tc);
+}
+
+#endif // __ARCH_X86_PSEUDO_INST_HH__
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index fa226ac55..dd0aed770 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -232,15 +232,22 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
 {
     Addr paddr = req->getPaddr();
 
-    // Check for an access to the local APIC
-    if (FullSystem) {
+    AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
+
+    if (m5opRange.contains(paddr)) {
+        if (m5opRange.contains(paddr)) {
+            req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
+            req->setPaddr(GenericISA::iprAddressPseudoInst(
+                            (paddr >> 8) & 0xFF,
+                            paddr & 0xFF));
+        }
+    } else if (FullSystem) {
+        // Check for an access to the local APIC
         LocalApicBase localApicBase =
             tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
         AddrRange apicRange(localApicBase.base * PageBytes,
                             (localApicBase.base + 1) * PageBytes - 1);
 
-        AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
-
         if (apicRange.contains(paddr)) {
             // The Intel developer's manuals say the below restrictions apply,
             // but the linux kernel, because of a compiler optimization, breaks
@@ -257,11 +264,6 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
             req->setFlags(Request::UNCACHEABLE);
             req->setPaddr(x86LocalAPICAddress(tc->contextId(),
                                               paddr - apicRange.start()));
-        } else if (m5opRange.contains(paddr)) {
-            req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
-            req->setPaddr(GenericISA::iprAddressPseudoInst(
-                              (paddr >> 8) & 0xFF,
-                              paddr & 0xFF));
         }
     }
 
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index d58498be2..f7d0f816e 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -52,9 +52,7 @@ namespace X86ISA {
 uint64_t
 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
-    if (!FullSystem) {
-        panic("getArgument() only implemented for full system mode.\n");
-    } else if (fp) {
+    if (fp) {
         panic("getArgument(): Floating point arguments not implemented\n");
     } else if (size != 8) {
         panic("getArgument(): Can only handle 64-bit arguments.\n");