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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:20:47 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:20:47 -0800 |
| commit | b035c917a5e0749cb4068d2de66331beda52d222 (patch) | |
| tree | 044fd111c87f0ddb7bfb251ecff7d3c44afec8f0 /src/arch/x86 | |
| parent | 28efb3c6e3c13b9673e9077fcc9d54d2d512f72a (diff) | |
| download | gem5-b035c917a5e0749cb4068d2de66331beda52d222.tar.xz | |
X86: Make the segment register reading microops use merge.
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py | 2 | ||||
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py index 8d66cc445..8203f7c2c 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py @@ -142,7 +142,7 @@ processCSDescriptor: # Here, we know we're -not- in 64 bit mode, so we should do the # appropriate/other RIP checks. # if temp_RIP > CS.limit throw #GP(0) - rdlimit t6, cs + rdlimit t6, cs, dataSize=8 subi t0, t1, t6, flags=(ECF,) fault "new GeneralProtection(0)", flags=(CECF,) diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index fd2a3a64f..1349a64c2 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -1052,22 +1052,22 @@ let {{ class Rdbase(SegOp): code = ''' - DestReg = SegBaseSrc1; + DestReg = merge(DestReg, SegBaseSrc1, dataSize); ''' class Rdlimit(SegOp): code = ''' - DestReg = SegLimitSrc1; + DestReg = merge(DestReg, SegLimitSrc1, dataSize); ''' class RdAttr(SegOp): code = ''' - DestReg = SegAttrSrc1; + DestReg = merge(DestReg, SegAttrSrc1, dataSize); ''' class Rdsel(SegOp): code = ''' - DestReg = SegSelSrc1; + DestReg = merge(DestReg, SegSelSrc1, dataSize); ''' class Rdval(RegOp): |