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authorGabe Black <gblack@eecs.umich.edu>2008-10-12 17:57:46 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-12 17:57:46 -0700
commitf245358343fb26ac976d15b8f2a023caa0f9ba0d (patch)
tree05fbddda0840cb8ae564f12e9a410617e866d19f /src/arch/x86
parentcefb768131b1d0582c5cbe83feaa97060dfe15af (diff)
downloadgem5-f245358343fb26ac976d15b8f2a023caa0f9ba0d.tar.xz
Get rid of old RegContext code.
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/regfile.cc5
-rw-r--r--src/arch/x86/regfile.hh2
-rw-r--r--src/arch/x86/types.hh11
3 files changed, 0 insertions, 18 deletions
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 78fde7474..7d01c4bb4 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -248,11 +248,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
UNSERIALIZE_SCALAR(nextRip);
}
-void RegFile::changeContext(RegContextParam param, RegContextVal val)
-{
- panic("changeContext not implemented for x86!\n");
-}
-
void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
panic("copyMiscRegs not implemented for x86!\n");
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index 3c2387346..75c0290d3 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -145,8 +145,6 @@ namespace X86ISA
const std::string &section);
public:
-
- void changeContext(RegContextParam param, RegContextVal val);
};
int flattenIntIndex(ThreadContext * tc, int reg);
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 90df38d13..29420352b 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -246,17 +246,6 @@ namespace X86ISA
MiscReg ctrlReg;
} AnyReg;
- //XXX This is very hypothetical. X87 instructions would need to
- //change their "context" constantly. It's also not clear how
- //this would be handled as far as out of order execution.
- //Maybe x87 instructions are in order?
- enum RegContextParam
- {
- CONTEXT_X87_TOP
- };
-
- typedef int RegContextVal;
-
typedef uint16_t RegIndex;
struct CoreSpecific {