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authorGabe Black <gblack@eecs.umich.edu>2008-01-12 06:39:15 -0500
committerGabe Black <gblack@eecs.umich.edu>2008-01-12 06:39:15 -0500
commit223e48e6ae651e6e99bc1fbb58ec30d7f88a6e32 (patch)
treee6e61a26f42455b2d3011aeba7cd0477a45d5c22 /src/arch/x86
parent0e394fdfa43ea3b50691402e1345e27ad6d011da (diff)
downloadgem5-223e48e6ae651e6e99bc1fbb58ec30d7f88a6e32.tar.xz
X86: Make the IO ports work using extra physical address lines. Add a serial port.
--HG-- extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/tlb.cc10
-rw-r--r--src/arch/x86/x86_traits.hh2
2 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 08c621615..2e6ea4a22 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -470,6 +470,16 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
//overlapping.
req->setPaddr(regNum * sizeof(MiscReg));
return NoFault;
+ } else if (prefix == IntAddrPrefixIO) {
+ // TODO If CPL > IOPL or in virtual mode, check the I/O permission
+ // bitmap in the TSS.
+
+ Addr IOPort = vaddr & ~IntAddrPrefixMask;
+ // Make sure the address fits in the expected 16 bit IO address
+ // space.
+ assert(!(IOPort & ~0xFFFF));
+ req->setPaddr(PhysAddrPrefixIO | IOPort);
+ return NoFault;
} else {
panic("Access to unrecognized internal address space %#x.\n",
prefix);
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index dd9258db0..dc71de500 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -87,6 +87,8 @@ namespace X86ISA
const Addr IntAddrPrefixCPUID = ULL(0x100000000);
const Addr IntAddrPrefixMSR = ULL(0x200000000);
const Addr IntAddrPrefixIO = ULL(0x300000000);
+
+ const Addr PhysAddrPrefixIO = ULL(0x1000000000000000);
}
#endif //__ARCH_X86_X86TRAITS_HH__