arch: cpu: Rename *FloatRegBits* to *FloatReg*.

Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.

Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 files changed, 13 insertions, 13 deletions

diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh
index 5cb0bdbb0..1fe871752 100644
--- a/src/arch/x86/insts/micromediaop.hh
+++ b/src/arch/x86/insts/micromediaop.hh
@@ -72,7 +72,7 @@ namespace X86ISA
         int
         numItems(int size) const
         {
-            return scalarOp() ? 1 : (sizeof(FloatRegBits) / size);
+            return scalarOp() ? 1 : (sizeof(FloatReg) / size);
         }
 
         bool
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index f9c6a9f9b..b8ceb02ac 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -245,7 +245,7 @@ let {{
                     src2, size, destSize, srcSize, ext)
         op_class = 'SimdMiscOp'
         code = '''
-            int items = sizeof(FloatRegBits) / srcSize;
+            int items = sizeof(FloatReg) / srcSize;
             int offset = imm8;
             if (bits(src1, 0) && (ext & 0x1))
                 offset -= items;
@@ -267,7 +267,7 @@ let {{
                     src2, size, destSize, srcSize, ext)
         op_class = 'SimdMiscOp'
         code = '''
-            int items = sizeof(FloatRegBits) / destSize;
+            int items = sizeof(FloatReg) / destSize;
             int offset = imm8;
             if (bits(dest, 0) && (ext & 0x1))
                 offset -= items;
@@ -289,7 +289,7 @@ let {{
                     "InstRegIndex(0)", size, destSize, srcSize, ext)
         op_class = 'SimdMiscOp'
         code = '''
-            int items = sizeof(FloatRegBits) / srcSize;
+            int items = sizeof(FloatReg) / srcSize;
             uint64_t result = 0;
             int offset = (ext & 0x1) ? items : 0;
             for (int i = 0; i < items; i++) {
@@ -325,7 +325,7 @@ let {{
             assert(srcSize == destSize);
             int size = srcSize;
             int sizeBits = size * 8;
-            int items = sizeof(FloatRegBits) / size;
+            int items = sizeof(FloatReg) / size;
             int options;
             int optionBits;
             if (size == 8) {
@@ -342,7 +342,7 @@ let {{
             for (int i = 0; i < items; i++) {
                 uint64_t resBits;
                 uint8_t lsel = sel & mask(optionBits);
-                if (lsel * size >= sizeof(FloatRegBits)) {
+                if (lsel * size >= sizeof(FloatReg)) {
                     lsel -= options / 2;
                     resBits = bits(FpSrcReg2_uqw,
                             (lsel + 1) * sizeBits - 1,
@@ -367,7 +367,7 @@ let {{
         code = '''
             assert(srcSize == destSize);
             int size = destSize;
-            int items = (sizeof(FloatRegBits) / size) / 2;
+            int items = (sizeof(FloatReg) / size) / 2;
             int offset = ext ? items : 0;
             uint64_t result = 0;
             for (int i = 0; i < items; i++) {
@@ -393,7 +393,7 @@ let {{
         op_class = 'SimdMiscOp'
         code = '''
             assert(srcSize == destSize * 2);
-            int items = (sizeof(FloatRegBits) / destSize);
+            int items = (sizeof(FloatReg) / destSize);
             int destBits = destSize * 8;
             int srcBits = srcSize * 8;
             uint64_t result = 0;
@@ -1091,7 +1091,7 @@ let {{
         op_class = 'SimdAddOp'
         code = '''
             int srcBits = srcSize * 8;
-            int items = sizeof(FloatRegBits) / srcSize;
+            int items = sizeof(FloatReg) / srcSize;
 
             uint64_t sum = 0;
             for (int i = 0; i < items; i++) {
diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
index d7472ef1f..142a51cd7 100644
--- a/src/arch/x86/nativetrace.cc
+++ b/src/arch/x86/nativetrace.cc
@@ -90,9 +90,9 @@ X86NativeTrace::ThreadState::update(ThreadContext *tc)
     rip = tc->pcState().npc();
     //This should be expanded if x87 registers are considered
     for (int i = 0; i < 8; i++)
-        mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
+        mmx[i] = tc->readFloatReg(X86ISA::FLOATREG_MMX(i));
     for (int i = 0; i < 32; i++)
-        xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
+        xmm[i] = tc->readFloatReg(X86ISA::FLOATREG_XMM_BASE + i);
 }
 
 
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 893822263..8b1d59426 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -117,7 +117,7 @@ constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
 //These floating point types are correct for mmx, but not
 //technically for x87 (80 bits) or at all for xmm (128 bits)
-typedef RegVal FloatRegBits;
+typedef RegVal FloatReg;
 
 } // namespace X86ISA
 
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 33b53ca92..b430124ec 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -239,7 +239,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
          dest->setIntRegFlat(i, src->readIntRegFlat(i));
     //copy float regs
     for (int i = 0; i < NumFloatRegs; ++i)
-         dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i));
+         dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
     //copy condition-code regs
     for (int i = 0; i < NumCCRegs; ++i)
          dest->setCCRegFlat(i, src->readCCRegFlat(i));