diff options
| author | Gabe Black <gabeblack@google.com> | 2019-09-02 21:26:12 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-10-19 01:45:48 +0000 |
| commit | ae390c629f2a10fd6a1c2eb50b7d3510d6e091da (patch) | |
| tree | 51f12635838755ef7519bea1c72bfb96e0214336 /src/arch/x86 | |
| parent | 1c047f8b92f5708bbef50d24cf47902d5da313e3 (diff) | |
| download | gem5-ae390c629f2a10fd6a1c2eb50b7d3510d6e091da.tar.xz | |
arch: Make a base class for Interrupts.
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.
Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/x86')
| -rw-r--r-- | src/arch/x86/X86LocalApic.py | 3 | ||||
| -rw-r--r-- | src/arch/x86/interrupts.cc | 2 | ||||
| -rw-r--r-- | src/arch/x86/interrupts.hh | 7 | ||||
| -rw-r--r-- | src/arch/x86/pagetable_walker.cc | 1 |
4 files changed, 8 insertions, 5 deletions
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py index 914f29766..b7ab7bc6d 100644 --- a/src/arch/x86/X86LocalApic.py +++ b/src/arch/x86/X86LocalApic.py @@ -42,10 +42,11 @@ from m5.defines import buildEnv from m5.params import * from m5.proxy import * +from m5.objects.BaseInterrupts import BaseInterrupts from m5.objects.ClockDomain import DerivedClockDomain from m5.SimObject import SimObject -class X86LocalApic(SimObject): +class X86LocalApic(BaseInterrupts): type = 'X86LocalApic' cxx_class = 'X86ISA::Interrupts' cxx_header = 'arch/x86/interrupts.hh' diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index d237366ab..80d2650ef 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -596,7 +596,7 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) X86ISA::Interrupts::Interrupts(Params * p) - : SimObject(p), sys(p->system), clockDomain(*p->clk_domain), + : BaseInterrupts(p), sys(p->system), clockDomain(*p->clk_domain), apicTimerEvent([this]{ processApicTimerEvent(); }, name()), pendingSmi(false), smiVector(0), pendingNmi(false), nmiVector(0), diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh index 519d9f10e..3c383ab92 100644 --- a/src/arch/x86/interrupts.hh +++ b/src/arch/x86/interrupts.hh @@ -53,13 +53,14 @@ #ifndef __ARCH_X86_INTERRUPTS_HH__ #define __ARCH_X86_INTERRUPTS_HH__ -#include "arch/x86/regs/apic.hh" +#include "arch/generic/interrupts.hh" #include "arch/x86/faults.hh" #include "arch/x86/intmessage.hh" +#include "arch/x86/regs/apic.hh" #include "base/bitfield.hh" #include "cpu/thread_context.hh" -#include "dev/x86/intdev.hh" #include "dev/io_device.hh" +#include "dev/x86/intdev.hh" #include "params/X86LocalApic.hh" #include "sim/eventq.hh" @@ -72,7 +73,7 @@ namespace X86ISA { ApicRegIndex decodeAddr(Addr paddr); -class Interrupts : public SimObject +class Interrupts : public BaseInterrupts { protected: System *sys; diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc index 86f140fdc..aab0a7118 100644 --- a/src/arch/x86/pagetable_walker.cc +++ b/src/arch/x86/pagetable_walker.cc @@ -53,6 +53,7 @@ #include <memory> +#include "arch/x86/faults.hh" #include "arch/x86/pagetable.hh" #include "arch/x86/tlb.hh" #include "arch/x86/vtophys.hh" |