x86: Stop using/defining some ISA specific register types.

These have been replaced with the generic RegVal type.

Change-Id: I75c1134212067dea43aa0903d813633e06f3d6c6
Reviewed-on: https://gem5-review.googlesource.com/c/14476
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

16 files changed, 76 insertions, 90 deletions

diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index c0b30b5e8..412b7c73f 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -222,7 +222,7 @@ class Decoder
   protected:
     /// Caching for decoded instruction objects.
 
-    typedef MiscReg CacheKey;
+    typedef RegVal CacheKey;
 
     typedef DecodeCache::AddrMap<Decoder::InstBytes> DecodePages;
     DecodePages *decodePages;
diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh
index 1fe871752..6bbfc510b 100644
--- a/src/arch/x86/insts/micromediaop.hh
+++ b/src/arch/x86/insts/micromediaop.hh
@@ -72,7 +72,7 @@ namespace X86ISA
         int
         numItems(int size) const
         {
-            return scalarOp() ? 1 : (sizeof(FloatReg) / size);
+            return scalarOp() ? 1 : (sizeof(uint64_t) / size);
         }
 
         bool
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index a866b950f..d96a85893 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -107,7 +107,7 @@ ISA::clear()
 {
     // Blank everything. 0 might not be an appropriate value for some things,
     // but it is for most.
-    memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
+    memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
     regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
     regVal[MISCREG_DR7] = 1 << 10;
 }
@@ -124,7 +124,7 @@ ISA::params() const
     return dynamic_cast<const Params *>(_params);
 }
 
-MiscReg
+RegVal
 ISA::readMiscRegNoEffect(int miscReg) const
 {
     // Make sure we're not dealing with an illegal control register.
@@ -135,7 +135,7 @@ ISA::readMiscRegNoEffect(int miscReg) const
     return regVal[miscReg];
 }
 
-MiscReg
+RegVal
 ISA::readMiscReg(int miscReg, ThreadContext * tc)
 {
     if (miscReg == MISCREG_TSC) {
@@ -143,8 +143,8 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
     }
 
     if (miscReg == MISCREG_FSW) {
-        MiscReg fsw = regVal[MISCREG_FSW];
-        MiscReg top = regVal[MISCREG_X87_TOP];
+        RegVal fsw = regVal[MISCREG_FSW];
+        RegVal top = regVal[MISCREG_X87_TOP];
         return insertBits(fsw, 13, 11, top);
     }
 
@@ -152,7 +152,7 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
 }
 
 void
-ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
+ISA::setMiscRegNoEffect(int miscReg, RegVal val)
 {
     // Make sure we're not dealing with an illegal control register.
     // Instructions should filter out these indexes, and nothing else should
@@ -194,9 +194,9 @@ ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
 }
 
 void
-ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
+ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
 {
-    MiscReg newVal = val;
+    RegVal newVal = val;
     switch(miscReg)
     {
       case MISCREG_CR0:
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 7ad464643..a835a794a 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -51,7 +51,7 @@ namespace X86ISA
     class ISA : public SimObject
     {
       protected:
-        MiscReg regVal[NUM_MISCREGS];
+        RegVal regVal[NUM_MISCREGS];
         void updateHandyM5Reg(Efer efer, CR0 cr0,
                 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
                 ThreadContext *tc);
@@ -64,11 +64,11 @@ namespace X86ISA
         ISA(Params *p);
         const Params *params() const;
 
-        MiscReg readMiscRegNoEffect(int miscReg) const;
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+        RegVal readMiscRegNoEffect(int miscReg) const;
+        RegVal readMiscReg(int miscReg, ThreadContext *tc);
 
-        void setMiscRegNoEffect(int miscReg, MiscReg val);
-        void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
+        void setMiscRegNoEffect(int miscReg, RegVal val);
+        void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
 
         RegId
         flattenRegId(const RegId& regId) const
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index 52193f2c0..97ed40629 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -380,7 +380,7 @@ let {{
 
     class PremFp(FpBinaryOp):
         code = '''
-            MiscReg new_fsw = FSW;
+            RegVal new_fsw = FSW;
             int src1_exp;
             int src2_exp;
             std::frexp(FpSrcReg1, &src1_exp);
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index b8ceb02ac..4bbe093a4 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -245,7 +245,7 @@ let {{
                     src2, size, destSize, srcSize, ext)
         op_class = 'SimdMiscOp'
         code = '''
-            int items = sizeof(FloatReg) / srcSize;
+            int items = sizeof(double) / srcSize;
             int offset = imm8;
             if (bits(src1, 0) && (ext & 0x1))
                 offset -= items;
@@ -267,7 +267,7 @@ let {{
                     src2, size, destSize, srcSize, ext)
         op_class = 'SimdMiscOp'
         code = '''
-            int items = sizeof(FloatReg) / destSize;
+            int items = sizeof(double) / destSize;
             int offset = imm8;
             if (bits(dest, 0) && (ext & 0x1))
                 offset -= items;
@@ -289,7 +289,7 @@ let {{
                     "InstRegIndex(0)", size, destSize, srcSize, ext)
         op_class = 'SimdMiscOp'
         code = '''
-            int items = sizeof(FloatReg) / srcSize;
+            int items = sizeof(double) / srcSize;
             uint64_t result = 0;
             int offset = (ext & 0x1) ? items : 0;
             for (int i = 0; i < items; i++) {
@@ -325,7 +325,7 @@ let {{
             assert(srcSize == destSize);
             int size = srcSize;
             int sizeBits = size * 8;
-            int items = sizeof(FloatReg) / size;
+            int items = sizeof(double) / size;
             int options;
             int optionBits;
             if (size == 8) {
@@ -342,7 +342,7 @@ let {{
             for (int i = 0; i < items; i++) {
                 uint64_t resBits;
                 uint8_t lsel = sel & mask(optionBits);
-                if (lsel * size >= sizeof(FloatReg)) {
+                if (lsel * size >= sizeof(double)) {
                     lsel -= options / 2;
                     resBits = bits(FpSrcReg2_uqw,
                             (lsel + 1) * sizeBits - 1,
@@ -367,7 +367,7 @@ let {{
         code = '''
             assert(srcSize == destSize);
             int size = destSize;
-            int items = (sizeof(FloatReg) / size) / 2;
+            int items = (sizeof(double) / size) / 2;
             int offset = ext ? items : 0;
             uint64_t result = 0;
             for (int i = 0; i < items; i++) {
@@ -393,7 +393,7 @@ let {{
         op_class = 'SimdMiscOp'
         code = '''
             assert(srcSize == destSize * 2);
-            int items = (sizeof(FloatReg) / destSize);
+            int items = (sizeof(double) / destSize);
             int destBits = destSize * 8;
             int srcBits = srcSize * 8;
             uint64_t result = 0;
@@ -1091,7 +1091,7 @@ let {{
         op_class = 'SimdAddOp'
         code = '''
             int srcBits = srcSize * 8;
-            int items = sizeof(FloatReg) / srcSize;
+            int items = sizeof(double) / srcSize;
 
             uint64_t sum = 0;
             for (int i = 0; i < items; i++) {
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 08a4ddd41..6f2901b25 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -51,7 +51,7 @@ def template MicroRegOpExecute {{
             %(op_decl)s;
             %(op_rd)s;
 
-            IntReg result M5_VAR_USED;
+            RegVal result M5_VAR_USED;
 
             if(%(cond_check)s)
             {
@@ -81,7 +81,7 @@ def template MicroRegOpImmExecute {{
             %(op_decl)s;
             %(op_rd)s;
 
-            IntReg result M5_VAR_USED;
+            RegVal result M5_VAR_USED;
 
             if(%(cond_check)s)
             {
@@ -1220,8 +1220,8 @@ let {{
 
     class Wrflags(WrRegOp):
         code = '''
-            MiscReg newFlags = psrc1 ^ op2;
-            MiscReg userFlagMask = 0xDD5;
+            RegVal newFlags = psrc1 ^ op2;
+            RegVal userFlagMask = 0xDD5;
 
             // Get only the user flags
             ccFlagBits = newFlags & ccFlagMask;
@@ -1268,8 +1268,8 @@ let {{
 
     class Rflag(RegOp):
         code = '''
-            MiscReg flagMask = 0x3F7FDD5;
-            MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
+            RegVal flagMask = 0x3F7FDD5;
+            RegVal flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
                              ecfBit | ezfBit) & flagMask;
 
             int flag = bits(flags, imm8);
@@ -1278,8 +1278,8 @@ let {{
             '''
 
         big_code = '''
-            MiscReg flagMask = 0x3F7FDD5;
-            MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
+            RegVal flagMask = 0x3F7FDD5;
+            RegVal flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
                              ecfBit | ezfBit) & flagMask;
 
             int flag = bits(flags, imm8);
@@ -1294,7 +1294,7 @@ let {{
 
     class Sext(RegOp):
         code = '''
-            IntReg val = psrc1;
+            RegVal val = psrc1;
             // Mask the bit position so that it wraps.
             int bitPos = op2 & (dataSize * 8 - 1);
             int sign_bit = bits(val, bitPos, bitPos);
@@ -1304,7 +1304,7 @@ let {{
             '''
 
         big_code = '''
-            IntReg val = psrc1;
+            RegVal val = psrc1;
             // Mask the bit position so that it wraps.
             int bitPos = op2 & (dataSize * 8 - 1);
             int sign_bit = bits(val, bitPos, bitPos);
@@ -1390,10 +1390,7 @@ let {{
             if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
                 fault = std::make_shared<InvalidOpcode>();
             } else {
-                // There are *s in the line below so it doesn't confuse the
-                // parser. They may be unnecessary.
-                //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
-                MiscReg newVal = psrc1;
+                RegVal newVal = psrc1;
 
                 // Check for any modifications that would cause a fault.
                 switch(dest) {
diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index 6a9aea85b..9e8997afc 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -549,7 +549,7 @@ X86_64LinuxProcess::X86_64LinuxProcess(ProcessParams * params,
 {}
 
 void X86_64LinuxProcess::clone(ThreadContext *old_tc, ThreadContext *new_tc,
-                               Process *process, TheISA::IntReg flags)
+                               Process *process, RegVal flags)
 {
     X86_64Process::clone(old_tc, new_tc, (X86_64Process*)process, flags);
 }
@@ -891,7 +891,7 @@ I386LinuxProcess::I386LinuxProcess(ProcessParams * params, ObjectFile *objFile)
 {}
 
 void I386LinuxProcess::clone(ThreadContext *old_tc, ThreadContext *new_tc,
-                             Process *process, TheISA::IntReg flags)
+                             Process *process, RegVal flags)
 {
     I386Process::clone(old_tc, new_tc, (I386Process*)process, flags);
 }
diff --git a/src/arch/x86/linux/process.hh b/src/arch/x86/linux/process.hh
index bafa9cc6c..d4c9b0cf6 100644
--- a/src/arch/x86/linux/process.hh
+++ b/src/arch/x86/linux/process.hh
@@ -55,7 +55,7 @@ class X86_64LinuxProcess : public X86_64Process
     /// Constructor.
     X86_64LinuxProcess(ProcessParams * params, ObjectFile *objFile);
     void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process *process,
-               TheISA::IntReg flags);
+               RegVal flags);
 };
 
 class I386LinuxProcess : public I386Process
@@ -64,7 +64,7 @@ class I386LinuxProcess : public I386Process
     /// Constructor.
     I386LinuxProcess(ProcessParams * params, ObjectFile *objFile);
     void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process *process,
-               TheISA::IntReg flags);
+               RegVal flags);
 };
 
 } // namespace X86ISA
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index bd24d33da..93c16d33d 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -62,10 +62,10 @@ namespace X86ISA
         } else {
             Addr offset = pkt->getAddr() & mask(3);
             MiscRegIndex index = (MiscRegIndex)(
-                pkt->getAddr() / sizeof(MiscReg));
-            MiscReg data = htog(xc->readMiscReg(index));
+                pkt->getAddr() / sizeof(RegVal));
+            RegVal data = htog(xc->readMiscReg(index));
             // Make sure we don't trot off the end of data.
-            assert(offset + pkt->getSize() <= sizeof(MiscReg));
+            assert(offset + pkt->getSize() <= sizeof(RegVal));
             pkt->setData(((uint8_t *)&data) + offset);
             return Cycles(1);
         }
@@ -79,11 +79,10 @@ namespace X86ISA
         } else {
             Addr offset = pkt->getAddr() & mask(3);
             MiscRegIndex index = (MiscRegIndex)(
-                pkt->getAddr() / sizeof(MiscReg));
-            MiscReg data;
-            data = htog(xc->readMiscRegNoEffect(index));
+                pkt->getAddr() / sizeof(RegVal));
+            RegVal data = htog(xc->readMiscRegNoEffect(index));
             // Make sure we don't trot off the end of data.
-            assert(offset + pkt->getSize() <= sizeof(MiscReg));
+            assert(offset + pkt->getSize() <= sizeof(RegVal));
             pkt->writeData(((uint8_t *)&data) + offset);
             xc->setMiscReg(index, gtoh(data));
             return Cycles(1);
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 273e2c0f9..04bc0ddc8 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -119,7 +119,7 @@ X86Process::X86Process(ProcessParams *params, ObjectFile *objFile,
 }
 
 void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
-                       Process *p, TheISA::IntReg flags)
+                       Process *p, RegVal flags)
 {
     Process::clone(old_tc, new_tc, p, flags);
     X86Process *process = (X86Process*)p;
@@ -444,11 +444,11 @@ X86_64Process::initState()
             tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
 
             /* enabling syscall and sysret */
-            MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32);
+            RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32);
             tc->setMiscReg(MISCREG_STAR, star);
-            MiscReg lstar = (MiscReg)syscallCodeVirtAddr;
+            RegVal lstar = (RegVal)syscallCodeVirtAddr;
             tc->setMiscReg(MISCREG_LSTAR, lstar);
-            MiscReg sfmask = (1 << 8) | (1 << 10); // TF | DF
+            RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF
             tc->setMiscReg(MISCREG_SF_MASK, sfmask);
         }
 
@@ -1070,7 +1070,7 @@ X86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval)
     tc->setIntReg(INTREG_RAX, retval.encodedValue());
 }
 
-X86ISA::IntReg
+RegVal
 X86_64Process::getSyscallArg(ThreadContext *tc, int &i)
 {
     assert(i < NumArgumentRegs);
@@ -1078,7 +1078,7 @@ X86_64Process::getSyscallArg(ThreadContext *tc, int &i)
 }
 
 void
-X86_64Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
+X86_64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
 {
     assert(i < NumArgumentRegs);
     return tc->setIntReg(ArgumentReg[i], val);
@@ -1086,20 +1086,20 @@ X86_64Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
 
 void
 X86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
-                     Process *p, TheISA::IntReg flags)
+                     Process *p, RegVal flags)
 {
     X86Process::clone(old_tc, new_tc, p, flags);
     ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
 }
 
-X86ISA::IntReg
+RegVal
 I386Process::getSyscallArg(ThreadContext *tc, int &i)
 {
     assert(i < NumArgumentRegs32);
     return tc->readIntReg(ArgumentReg32[i++]);
 }
 
-X86ISA::IntReg
+RegVal
 I386Process::getSyscallArg(ThreadContext *tc, int &i, int width)
 {
     assert(width == 32 || width == 64);
@@ -1111,7 +1111,7 @@ I386Process::getSyscallArg(ThreadContext *tc, int &i, int width)
 }
 
 void
-I386Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
+I386Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
 {
     assert(i < NumArgumentRegs);
     return tc->setIntReg(ArgumentReg[i], val);
@@ -1119,7 +1119,7 @@ I386Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val)
 
 void
 I386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
-                   Process *p, TheISA::IntReg flags)
+                   Process *p, RegVal flags)
 {
     X86Process::clone(old_tc, new_tc, p, flags);
     ((I386Process*)p)->vsyscallPage = vsyscallPage;
diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh
index 31706cfdd..9c2ec6506 100644
--- a/src/arch/x86/process.hh
+++ b/src/arch/x86/process.hh
@@ -92,7 +92,7 @@ namespace X86ISA
         void setSyscallReturn(ThreadContext *tc,
                               SyscallReturn return_value) override;
         void clone(ThreadContext *old_tc, ThreadContext *new_tc,
-                   Process *process, TheISA::IntReg flags) override;
+                   Process *process, RegVal flags) override;
 
         X86Process &
         operator=(const X86Process &in)
@@ -142,13 +142,12 @@ namespace X86ISA
         void argsInit(int pageSize);
         void initState() override;
 
-        X86ISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
+        RegVal getSyscallArg(ThreadContext *tc, int &i) override;
         /// Explicitly import the otherwise hidden getSyscallArg
         using Process::getSyscallArg;
-        void setSyscallArg(ThreadContext *tc, int i,
-                           X86ISA::IntReg val) override;
+        void setSyscallArg(ThreadContext *tc, int i, RegVal val) override;
         void clone(ThreadContext *old_tc, ThreadContext *new_tc,
-                   Process *process, TheISA::IntReg flags) override;
+                   Process *process, RegVal flags) override;
     };
 
     class I386Process : public X86Process
@@ -187,14 +186,11 @@ namespace X86ISA
 
         void syscall(int64_t callnum, ThreadContext *tc,
                      Fault *fault) override;
-        X86ISA::IntReg getSyscallArg(ThreadContext *tc,
-                                     int &i) override;
-        X86ISA::IntReg getSyscallArg(ThreadContext *tc, int &i,
-                                     int width) override;
-        void setSyscallArg(ThreadContext *tc, int i,
-                           X86ISA::IntReg val) override;
+        RegVal getSyscallArg(ThreadContext *tc, int &i) override;
+        RegVal getSyscallArg(ThreadContext *tc, int &i, int width) override;
+        void setSyscallArg(ThreadContext *tc, int i, RegVal val) override;
         void clone(ThreadContext *old_tc, ThreadContext *new_tc,
-                   Process *process, TheISA::IntReg flags) override;
+                   Process *process, RegVal flags) override;
     };
 
 }
diff --git a/src/arch/x86/pseudo_inst.cc b/src/arch/x86/pseudo_inst.cc
index c0ec11059..90000b808 100644
--- a/src/arch/x86/pseudo_inst.cc
+++ b/src/arch/x86/pseudo_inst.cc
@@ -52,7 +52,7 @@ m5Syscall(ThreadContext *tc)
     Fault fault;
     tc->syscall(tc->readIntReg(INTREG_RAX), &fault);
 
-    MiscReg rflags = tc->readMiscReg(MISCREG_RFLAGS);
+    RegVal rflags = tc->readMiscReg(MISCREG_RFLAGS);
     rflags &= ~(1 << 16);
     tc->setMiscReg(MISCREG_RFLAGS, rflags);
 }
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 8b1d59426..ea75ec907 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -96,9 +96,7 @@ const int FramePointerReg = INTREG_RBP;
 // value
 const int SyscallPseudoReturnReg = INTREG_RDX;
 
-typedef RegVal IntReg;
 typedef uint64_t CCReg;
-typedef RegVal MiscReg;
 
 // Not applicable to x86
 using VecElem = ::DummyVecElem;
@@ -115,10 +113,6 @@ using VecPredRegContainer = ::DummyVecPredRegContainer;
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
 constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
-//These floating point types are correct for mmx, but not
-//technically for x87 (80 bits) or at all for xmm (128 bits)
-typedef RegVal FloatReg;
-
 } // namespace X86ISA
 
 #endif // __ARCH_X86_REGFILE_HH__
diff --git a/src/arch/x86/system.cc b/src/arch/x86/system.cc
index 0f85fdb38..3f44ece3a 100644
--- a/src/arch/x86/system.cc
+++ b/src/arch/x86/system.cc
@@ -100,7 +100,7 @@ X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
     tc->setMiscReg(MISCREG_SEG_BASE(seg), desc.base);
     tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? desc.base : 0);
     tc->setMiscReg(MISCREG_SEG_LIMIT(seg), desc.limit);
-    tc->setMiscReg(MISCREG_SEG_ATTR(seg), (MiscReg)attr);
+    tc->setMiscReg(MISCREG_SEG_ATTR(seg), (RegVal)attr);
 }
 
 void
@@ -175,7 +175,7 @@ X86System::initState()
     SegSelector cs = 0;
     cs.si = numGDTEntries - 1;
 
-    tc->setMiscReg(MISCREG_CS, (MiscReg)cs);
+    tc->setMiscReg(MISCREG_CS, (RegVal)cs);
 
     // 32 bit data segment
     SegDescriptor dsDesc = initDesc;
@@ -188,11 +188,11 @@ X86System::initState()
     SegSelector ds = 0;
     ds.si = numGDTEntries - 1;
 
-    tc->setMiscReg(MISCREG_DS, (MiscReg)ds);
-    tc->setMiscReg(MISCREG_ES, (MiscReg)ds);
-    tc->setMiscReg(MISCREG_FS, (MiscReg)ds);
-    tc->setMiscReg(MISCREG_GS, (MiscReg)ds);
-    tc->setMiscReg(MISCREG_SS, (MiscReg)ds);
+    tc->setMiscReg(MISCREG_DS, (RegVal)ds);
+    tc->setMiscReg(MISCREG_ES, (RegVal)ds);
+    tc->setMiscReg(MISCREG_FS, (RegVal)ds);
+    tc->setMiscReg(MISCREG_GS, (RegVal)ds);
+    tc->setMiscReg(MISCREG_SS, (RegVal)ds);
 
     tc->setMiscReg(MISCREG_TSL, 0);
     tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
@@ -208,7 +208,7 @@ X86System::initState()
     SegSelector tss = 0;
     tss.si = numGDTEntries - 1;
 
-    tc->setMiscReg(MISCREG_TR, (MiscReg)tss);
+    tc->setMiscReg(MISCREG_TR, (RegVal)tss);
     installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true);
 
     /*
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 8e83208f4..589b2b7eb 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -185,10 +185,10 @@ TLB::translateInt(const RequestPtr &req, ThreadContext *tc)
         if (!msrAddrToIndex(regNum, vaddr))
             return std::make_shared<GeneralProtection>(0);
 
-        //The index is multiplied by the size of a MiscReg so that
+        //The index is multiplied by the size of a RegVal so that
         //any memory dependence calculations will not see these as
         //overlapping.
-        req->setPaddr((Addr)regNum * sizeof(MiscReg));
+        req->setPaddr((Addr)regNum * sizeof(RegVal));
         return NoFault;
     } else if (prefix == IntAddrPrefixIO) {
         // TODO If CPL > IOPL or in virtual mode, check the I/O permission
@@ -200,7 +200,7 @@ TLB::translateInt(const RequestPtr &req, ThreadContext *tc)
         assert(!(IOPort & ~0xFFFF));
         if (IOPort == 0xCF8 && req->getSize() == 4) {
             req->setFlags(Request::MMAPPED_IPR);
-            req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
+            req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal));
         } else if ((IOPort & ~mask(2)) == 0xCFC) {
             req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
             Addr configAddress =