arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL

Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

7 files changed, 11 insertions, 13 deletions

diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 03a758ff9..1f849b971 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -703,7 +703,7 @@ ArmStaticInst::checkAdvSIMDOrFPEnabled32(ThreadContext *tc,
     const bool have_virtualization = ArmSystem::haveVirtualization(tc);
     const bool have_security = ArmSystem::haveSecurity(tc);
     const bool is_secure = inSecureState(tc);
-    const ExceptionLevel cur_el = opModeToEL(currOpMode(tc));
+    const ExceptionLevel cur_el = currEL(tc);
 
     if (cur_el == EL0 && ELIs64(tc, EL1))
         return checkFPAdvSIMDEnabled64(tc, cpsr, cpacr);
diff --git a/src/arch/arm/isa/insts/branch64.isa b/src/arch/arm/isa/insts/branch64.isa
index 8ef9f934e..356114ec7 100644
--- a/src/arch/arm/isa/insts/branch64.isa
+++ b/src/arch/arm/isa/insts/branch64.isa
@@ -103,7 +103,7 @@ let {{
                 CPSR cpsr = Cpsr;
                 CPSR spsr = Spsr;
 
-                ExceptionLevel curr_el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
+                ExceptionLevel curr_el = currEL(cpsr);
                 switch (curr_el) {
                   case EL3:
                     newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL3);
@@ -145,7 +145,7 @@ let {{
                 NextAArch64 = !new_cpsr.width;
                 NextItState = itState(new_cpsr);
                 NPC = purifyTaggedAddr(newPc, xc->tcBase(),
-                    opModeToEL((OperatingMode) (uint8_t) new_cpsr.mode));
+                    currEL(new_cpsr));
 
                 LLSCLock = 0;  // Clear exclusive monitor
                 SevMailbox = 1; //Set Event Register
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index 6b2e8cc77..cc8e6844c 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -114,7 +114,7 @@ let {{
 
             auto tc = xc->tcBase();
             if (badMode32(tc, static_cast<OperatingMode>(regMode))) {
-                return undefinedFault32(tc, opModeToEL(currOpMode(tc)));
+                return undefinedFault32(tc, currEL(tc));
             }
 
             CPSR cpsr = Cpsr;
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 7283b205f..87cc3fde3 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1117,7 +1117,7 @@ canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 
     bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
 
-    switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
+    switch (currEL(cpsr)) {
       case EL0:
         return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
             miscRegInfo[reg][MISCREG_USR_NS_RD];
@@ -1140,7 +1140,7 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
     // Check for SP_EL0 access while SPSEL == 0
     if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
         return false;
-    ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
+    ExceptionLevel el = currEL(cpsr);
     if (reg == MISCREG_DAIF) {
         SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
         if (el == EL0 && !sctlr.uma)
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 93d4f5efb..d5c0eccdd 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -499,7 +499,7 @@ PMU::CounterState::isFiltered() const
     const PMEVTYPER_t filter(this->filter);
     const SCR scr(pmu.isa->readMiscRegNoEffect(MISCREG_SCR));
     const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
-    const ExceptionLevel el(opModeToEL((OperatingMode)(uint8_t)cpsr.mode));
+    const ExceptionLevel el(currEL(cpsr));
     const bool secure(inSecureState(scr, cpsr));
 
     switch (el) {
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 848bd5b26..a2737b946 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1428,7 +1428,7 @@ TLB::tranTypeEL(CPSR cpsr, ArmTranslationType type)
       case S1CTran:
       case S1S2NsTran:
       case HypMode:
-        return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
+        return currEL(cpsr);
 
       default:
         panic("Unknown translation mode!\n");
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 73537a89c..924024d0e 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -225,9 +225,7 @@ longDescFormatInUse(ThreadContext *tc)
 RegVal
 readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
 {
-    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
-    const ExceptionLevel current_el =
-        opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
+    const ExceptionLevel current_el = currEL(tc);
 
     const bool is_secure = isSecureBelowEL3(tc);
 
@@ -356,7 +354,7 @@ ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
 bool
 isBigEndian64(ThreadContext *tc)
 {
-    switch (opModeToEL(currOpMode(tc))) {
+    switch (currEL(tc)) {
       case EL3:
         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
       case EL2:
@@ -820,7 +818,7 @@ decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
 bool
 SPAlignmentCheckEnabled(ThreadContext* tc)
 {
-    switch (opModeToEL(currOpMode(tc))) {
+    switch (currEL(tc)) {
       case EL3:
         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
       case EL2: