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authorGabe Black <gblack@eecs.umich.edu>2008-06-12 00:45:22 -0400
committerGabe Black <gblack@eecs.umich.edu>2008-06-12 00:45:22 -0400
commit254cc076500ab7ee382d76a92db3a5a3c2ec1e62 (patch)
treea3d48203470bf01ec0f5350fac226b2b890e016e /src/arch
parentf6a97752b04b14b7b7a37d29babc3030b3ec9ac4 (diff)
downloadgem5-254cc076500ab7ee382d76a92db3a5a3c2ec1e62.tar.xz
X86: Fix a byte register indexing issue in the sign extending move from memory microcode.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/move.py10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
index 3b8608c48..16196bcc8 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2007 The Hewlett-Packard Development Company
+# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use of this software in source and binary forms,
@@ -130,14 +130,14 @@ def macroop MOVSX_B_R_R {
};
def macroop MOVSX_B_R_M {
- ld reg, seg, sib, disp, dataSize=1
- sexti reg, reg, 7
+ ld t1, seg, sib, disp, dataSize=1
+ sexti reg, t1, 7
};
def macroop MOVSX_B_R_P {
rdip t7
- ld reg, seg, riprel, disp, dataSize=1
- sexti reg, reg, 7
+ ld t1, seg, riprel, disp, dataSize=1
+ sexti reg, t1, 7
};
def macroop MOVSX_W_R_R {