Registers: Add an ISA object which replaces the MiscRegFile.

This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.

34 files changed, 969 insertions, 396 deletions

diff --git a/src/arch/SConscript b/src/arch/SConscript
index 0d801fcad..a67cf869a 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -46,6 +46,7 @@ isa_switch_hdrs = Split('''
         arguments.hh
         faults.hh
         interrupts.hh
+	isa.hh
         isa_traits.hh
         kernel_stats.hh
         locked_mem.hh
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 069db2551..b10885e01 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -37,6 +37,7 @@ if env['TARGET_ISA'] == 'alpha':
     Source('floatregfile.cc')
     Source('intregfile.cc')
     Source('ipr.cc')
+    Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
     Source('regfile.cc')
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
new file mode 100644
index 000000000..ed452cfc6
--- /dev/null
+++ b/src/arch/alpha/isa.cc
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/alpha/isa.hh"
+#include "cpu/thread_context.hh"
+
+namespace AlphaISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+void
+ISA::serialize(std::ostream &os)
+{
+    miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(Checkpoint *cp, const std::string &section)
+{
+    miscRegFile.unserialize(cp, section);
+}
+
+}
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
new file mode 100644
index 000000000..4c19659ab
--- /dev/null
+++ b/src/arch/alpha/isa.hh
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_ALPHA_ISA_HH__
+#define __ARCH_ALPHA_ISA_HH__
+
+#include "arch/alpha/miscregfile.hh"
+#include "arch/alpha/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace AlphaISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+
+        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
+        {
+            miscRegFile.expandForMultithreading(num_threads, num_vpes);
+        }
+
+        void reset(std::string core_name, ThreadID num_threads,
+                unsigned num_vpes, BaseCPU *_cpu)
+        {
+            miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
+        }
+
+        int instAsid()
+        {
+            return miscRegFile.getInstAsid();
+        }
+
+        int dataAsid()
+        {
+            return miscRegFile.getDataAsid();
+        }
+
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int
+        flattenIntIndex(int reg)
+        {
+            return reg;
+        }
+
+        int
+        flattenFloatIndex(int reg)
+        {
+            return reg;
+        }
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+        ISA()
+        {
+            clear();
+        }
+    };
+}
+
+#endif
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index aea44976c..d2b37590a 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -55,6 +55,7 @@ output header {{
 output decoder {{
 #include <cmath>
 
+#include "arch/alpha/miscregfile.hh"
 #include "base/cprintf.hh"
 #include "base/fenv.hh"
 #include "base/loader/symtab.hh"
@@ -71,6 +72,7 @@ output exec {{
 #include "base/cp_annotate.hh"
 #include "sim/pseudo_inst.hh"
 #include "arch/alpha/ipr.hh"
+#include "arch/alpha/miscregfile.hh"
 #include "base/fenv.hh"
 #include "config/ss_compatible_fp.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index b3aa55b19..9009381b8 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -31,6 +31,7 @@
  */
 
 #include "arch/alpha/regfile.hh"
+#include "arch/alpha/miscregfile.hh"
 #include "cpu/thread_context.hh"
 
 using namespace std;
@@ -42,7 +43,6 @@ RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
     floatRegFile.serialize(os);
-    miscRegFile.serialize(os);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
@@ -55,7 +55,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
     floatRegFile.unserialize(cp, section);
-    miscRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index cbd3657f7..59b76efd5 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -93,23 +93,10 @@ class RegFile {
   protected:
     IntRegFile intRegFile;          // (signed) integer register file
     FloatRegFile floatRegFile;      // floating point register file
-    MiscRegFile miscRegFile;        // control register file
 
   public:
 #if FULL_SYSTEM
     int intrflag;                   // interrupt flag
-
-    int
-    instAsid()
-    {
-        return miscRegFile.getInstAsid();
-    }
-
-    int
-    dataAsid()
-    {
-        return miscRegFile.getDataAsid();
-    }
 #endif // FULL_SYSTEM
 
     void
@@ -117,31 +104,6 @@ class RegFile {
     {
         intRegFile.clear();
         floatRegFile.clear();
-        miscRegFile.clear();
-    }
-
-    MiscReg
-    readMiscRegNoEffect(int miscReg)
-    {
-        return miscRegFile.readRegNoEffect(miscReg);
-    }
-
-    MiscReg
-    readMiscReg(int miscReg, ThreadContext *tc)
-    {
-        return miscRegFile.readReg(miscReg, tc);
-    }
-
-    void
-    setMiscRegNoEffect(int miscReg, const MiscReg &val)
-    {
-        miscRegFile.setRegNoEffect(miscReg, val);
-    }
-
-    void
-    setMiscReg(int miscReg, const MiscReg &val, ThreadContext *tc)
-    {
-        miscRegFile.setReg(miscReg, val, tc);
     }
 
     FloatReg
@@ -209,18 +171,6 @@ class RegFile {
         const std::string &section);
 };
 
-static inline int
-flattenIntIndex(ThreadContext * tc, int reg)
-{
-    return reg;
-}
-
-static inline int
-flattenFloatIndex(ThreadContext * tc, int reg)
-{
-    return reg;
-}
-
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 
 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 60a5ca3b0..a88a911f7 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -39,6 +39,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/mem.cc')
     Source('insts/pred_inst.cc')
     Source('insts/static_inst.cc')
+    Source('isa.cc')
     Source('pagetable.cc')
     Source('regfile/regfile.cc')
     Source('tlb.cc')
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
new file mode 100644
index 000000000..944f19c0b
--- /dev/null
+++ b/src/arch/arm/isa.cc
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/arm/isa.hh"
+#include "cpu/thread_context.hh"
+
+namespace ArmISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect(miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg(miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect(miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg(miscReg, val, tc);
+}
+
+void
+ISA::serialize(std::ostream &os)
+{
+    //miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(Checkpoint *cp, const std::string &section)
+{
+    //miscRegFile.unserialize(cp, section);
+}
+
+}
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
new file mode 100644
index 000000000..cb207bf13
--- /dev/null
+++ b/src/arch/arm/isa.hh
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_ARM_ISA_HH__
+#define __ARCH_MRM_ISA_HH__
+
+#include "arch/arm/regfile/misc_regfile.hh"
+#include "arch/arm/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace ArmISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int
+        flattenIntIndex(int reg)
+        {
+            return reg;
+        }
+
+        int
+        flattenFloatIndex(int reg)
+        {
+            return reg;
+        }
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+        ISA()
+        {
+            clear();
+        }
+    };
+}
+
+#endif
diff --git a/src/arch/arm/regfile/misc_regfile.hh b/src/arch/arm/regfile/misc_regfile.hh
index f7e5fbd98..eda0e8f05 100644
--- a/src/arch/arm/regfile/misc_regfile.hh
+++ b/src/arch/arm/regfile/misc_regfile.hh
@@ -31,6 +31,7 @@
 #ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
 #define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
 
+#include "arch/arm/isa_traits.hh"
 #include "arch/arm/types.hh"
 #include "sim/faults.hh"
 
diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc
index a4d6e9a4a..9821630e3 100644
--- a/src/arch/arm/regfile/regfile.cc
+++ b/src/arch/arm/regfile/regfile.cc
@@ -59,11 +59,6 @@ RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
     //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
-    //SERIALZE_ARRAY(miscRegFile);
-    //SERIALIZE_SCALAR(miscRegs.fpcr);
-    //SERIALIZE_SCALAR(miscRegs.lock_flag);
-    //SERIALIZE_SCALAR(miscRegs.lock_addr);
-    //SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
 }
@@ -73,14 +68,8 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
     //UNSERIALIZE_ARRAY(floatRegFile);
-    //UNSERIALZE_ARRAY(miscRegFile);
-    //UNSERIALIZE_SCALAR(miscRegs.fpcr);
-    //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
-    //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
-    //UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
-
 }
 
 } // namespace ArmISA
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
index 5a812fecf..c432c0c28 100644
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -48,7 +48,6 @@ namespace ArmISA
       protected:
         IntRegFile intRegFile;		// (signed) integer register file
         FloatRegFile floatRegFile;	// floating point register file
-        MiscRegFile miscRegFile;	// control register file
 
       public:
 
@@ -56,28 +55,6 @@ namespace ArmISA
         {
             intRegFile.clear();
             floatRegFile.clear();
-            miscRegFile.clear();
-        }
-
-        MiscReg readMiscRegNoEffect(int miscReg)
-        {
-            return miscRegFile.readRegNoEffect(miscReg);
-        }
-
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc)
-        {
-            return miscRegFile.readReg(miscReg, tc);
-        }
-
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val)
-        {
-            miscRegFile.setRegNoEffect(miscReg, val);
-        }
-
-        void setMiscReg(int miscReg, const MiscReg &val,
-                ThreadContext * tc)
-        {
-            miscRegFile.setReg(miscReg, val, tc);
         }
 
         FloatRegVal readFloatReg(int floatReg)
@@ -171,22 +148,8 @@ namespace ArmISA
         void serialize(EventManager *em, std::ostream &os);
         void unserialize(EventManager *em, Checkpoint *cp,
                          const std::string &section);
-
-        void changeContext(RegContextParam param, RegContextVal val)
-        {
-        }
     };
 
-    static inline int flattenIntIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
-    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
     void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 0b470def6..a88829eae 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -34,6 +34,7 @@ Import('*')
 
 if env['TARGET_ISA'] == 'mips':
     Source('faults.cc')
+    Source('isa.cc')
     Source('regfile/int_regfile.cc')
     Source('regfile/float_regfile.cc')
     Source('regfile/misc_regfile.cc')
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
new file mode 100644
index 000000000..175374ca9
--- /dev/null
+++ b/src/arch/mips/isa.cc
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/mips/isa.hh"
+#include "arch/mips/regfile/misc_regfile.hh"
+#include "cpu/thread_context.hh"
+
+namespace MipsISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect(miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg(miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect(miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg(miscReg, val, tc);
+}
+
+void
+ISA::serialize(std::ostream &os)
+{
+    //miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(Checkpoint *cp, const std::string &section)
+{
+    //miscRegFile.unserialize(cp, section);
+}
+
+}
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
new file mode 100644
index 000000000..fd831834c
--- /dev/null
+++ b/src/arch/mips/isa.hh
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_MIPS_ISA_HH__
+#define __ARCH_MIPS_ISA_HH__
+
+#include "arch/mips/regfile/misc_regfile.hh"
+#include "arch/mips/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace MipsISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+
+        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
+        {
+            miscRegFile.expandForMultithreading(num_threads, num_vpes);
+        }
+
+        void reset(std::string core_name, ThreadID num_threads,
+                unsigned num_vpes, BaseCPU *_cpu)
+        {
+            miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
+        }
+
+        int instAsid()
+        {
+            return miscRegFile.getInstAsid();
+        }
+
+        int dataAsid()
+        {
+            return miscRegFile.getDataAsid();
+        }
+
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int
+        flattenIntIndex(int reg)
+        {
+            return reg;
+        }
+
+        int
+        flattenFloatIndex(int reg)
+        {
+            return reg;
+        }
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+        ISA()
+        {
+            clear();
+        }
+    };
+}
+
+#endif
diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc
index 908302866..4cc6725f7 100644
--- a/src/arch/mips/regfile.cc
+++ b/src/arch/mips/regfile.cc
@@ -193,11 +193,6 @@ RegFile::unserialize(Checkpoint *cp, const std::string &section)
 
 }
 
-static inline int flattenIntIndex(ThreadContext * tc, int reg)
-{
-    return reg;
-}
-
 void
 MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 {
diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc
index 975fad963..2b70ea9bd 100644
--- a/src/arch/mips/regfile/regfile.cc
+++ b/src/arch/mips/regfile/regfile.cc
@@ -42,7 +42,6 @@ RegFile::clear()
 {
     intRegFile.clear();
     floatRegFile.clear();
-    miscRegFile.clear();
 }
 
 void
@@ -51,7 +50,6 @@ RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
 {
     bzero(&intRegFile, sizeof(intRegFile));
     bzero(&floatRegFile, sizeof(floatRegFile));
-    miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
 }
 
 IntReg
@@ -66,31 +64,6 @@ RegFile::setIntReg(int intReg, const IntReg &val)
     return intRegFile.setReg(intReg, val);
 }
 
-MiscReg
-RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid)
-{
-    return miscRegFile.readRegNoEffect(miscReg, tid);
-}
-
-MiscReg
-RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid)
-{
-    return miscRegFile.readReg(miscReg, tc, tid);
-}
-
-void
-RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid)
-{
-    miscRegFile.setRegNoEffect(miscReg, val, tid);
-}
-
-void
-RegFile::setMiscReg(int miscReg, const MiscReg &val,
-                    ThreadContext *tc, ThreadID tid)
-{
-    miscRegFile.setReg(miscReg, val, tc, tid);
-}
-
 FloatRegVal
 RegFile::readFloatReg(int floatReg)
 {
@@ -144,17 +117,6 @@ RegFile::setShadowSet(int css){
     intRegFile.setShadowSet(css);
 }
 
-int
-RegFile::instAsid()
-{
-    return miscRegFile.getInstAsid();
-}
-
-int
-RegFile::dataAsid()
-{
-    return miscRegFile.getDataAsid();
-}
 
 Addr
 RegFile::readPC()
@@ -197,10 +159,6 @@ RegFile::serialize(EventManager *em, std::ostream &os)
 {
     intRegFile.serialize(os);
     //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
-    //SERIALZE_ARRAY(miscRegFile);
-    //SERIALIZE_SCALAR(miscRegs.fpcr);
-    //SERIALIZE_SCALAR(miscRegs.lock_flag);
-    //SERIALIZE_SCALAR(miscRegs.lock_addr);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
@@ -212,14 +170,9 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp,
 {
     intRegFile.unserialize(cp, section);
     //UNSERIALIZE_ARRAY(floatRegFile);
-    //UNSERIALZE_ARRAY(miscRegFile);
-    //UNSERIALIZE_SCALAR(miscRegs.fpcr);
-    //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
-    //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
-
 }
 
 } // namespace MipsISA
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 91951b078..b05f513b4 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -37,7 +37,6 @@
 //#include "arch/mips/mt.hh"
 #include "arch/mips/regfile/int_regfile.hh"
 #include "arch/mips/regfile/float_regfile.hh"
-#include "arch/mips/regfile/misc_regfile.hh"
 //#include "cpu/base.hh"
 #include "sim/faults.hh"
 
@@ -57,26 +56,16 @@ namespace MipsISA
 
         IntRegFile intRegFile;          // (signed) integer register file
         FloatRegFile floatRegFile;      // floating point register file
-        MiscRegFile miscRegFile;        // control register file
 
       public:
         void clear();
         void reset(std::string core_name, ThreadID num_threads,
                    unsigned num_vpes, BaseCPU *_cpu);
-        MiscRegFile *getMiscRegFilePtr();
 
         IntReg readIntReg(int intReg);
         Fault setIntReg(int intReg, const IntReg &val);
 
 
-        MiscReg readMiscRegNoEffect(int miscReg, ThreadID tid = 0);
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc,
-                            ThreadID tid = 0);
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val,
-                                ThreadID tid = 0);
-        void setMiscReg(int miscReg, const MiscReg &val,
-                        ThreadContext *tc, ThreadID tid = 0);
-
         FloatRegVal readFloatReg(int floatReg);
         FloatRegVal readFloatReg(int floatReg, int width);
         FloatRegBits readFloatRegBits(int floatReg);
@@ -89,9 +78,6 @@ namespace MipsISA
 
         void setShadowSet(int css);
 
-        int instAsid();
-        int dataAsid();
-
       public:
         Addr readPC();
         void setPC(Addr val);
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 1c77b6ff2..a88c77db9 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -98,17 +98,6 @@ namespace MipsISA {
     //
     //  Register File Utility Functions
     //
-    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
-    static inline int flattenIntIndex(ThreadContext * tc, int reg)
-    {
-        // Implement Shadow Sets Stuff Here;
-        return reg;
-    }
-
     static inline MachInst makeRegisterCopy(int dest, int src) {
         panic("makeRegisterCopy not implemented");
         return 0;
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 940cf2076..eb0d21598 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -36,6 +36,7 @@ if env['TARGET_ISA'] == 'sparc':
     Source('faults.cc')
     Source('floatregfile.cc')
     Source('intregfile.cc')
+    Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
     Source('regfile.cc')
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
new file mode 100644
index 000000000..3aeeb14ab
--- /dev/null
+++ b/src/arch/sparc/isa.cc
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/sparc/isa.hh"
+#include "cpu/thread_context.hh"
+
+namespace SparcISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+int
+ISA::flattenIntIndex(int reg)
+{
+    int gl = miscRegFile.readRegNoEffect(MISCREG_GL);
+    int cwp = miscRegFile.readRegNoEffect(MISCREG_CWP);
+    //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
+    int newReg;
+    //The total number of global registers
+    int numGlobals = (MaxGL + 1) * 8;
+    if(reg < 8)
+    {
+        //Global register
+        //Put it in the appropriate set of globals
+        newReg = reg + gl * 8;
+    }
+    else if(reg < NumIntArchRegs)
+    {
+        //Regular windowed register
+        //Put it in the window pointed to by cwp
+        newReg = numGlobals +
+            ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
+    }
+    else if(reg < NumIntArchRegs + NumMicroIntRegs)
+    {
+        //Microcode register
+        //Displace from the end of the regular registers
+        newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
+    }
+    else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
+    {
+        reg -= (NumIntArchRegs + NumMicroIntRegs);
+        if(reg < 8)
+        {
+            //Global register from the next window
+            //Put it in the appropriate set of globals
+            newReg = reg + gl * 8;
+        }
+        else
+        {
+            //Windowed register from the previous window
+            //Put it in the window before the one pointed to by cwp
+            newReg = numGlobals +
+                ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
+        }
+    }
+    else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
+    {
+        reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
+        if(reg < 8)
+        {
+            //Global register from the previous window
+            //Put it in the appropriate set of globals
+            newReg = reg + gl * 8;
+        }
+        else
+        {
+            //Windowed register from the next window
+            //Put it in the window after the one pointed to by cwp
+            newReg = numGlobals +
+                ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
+        }
+    }
+    else
+        panic("Tried to flatten invalid register index %d!\n", reg);
+    DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg);
+    return newReg;
+}
+
+void
+ISA::serialize(EventManager *em, std::ostream &os)
+{
+    miscRegFile.serialize(em, os);
+}
+
+void
+ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
+{
+    miscRegFile.unserialize(em, cp, section);
+}
+
+}
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
new file mode 100644
index 000000000..1dbfe7a28
--- /dev/null
+++ b/src/arch/sparc/isa.hh
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_SPARC_ISA_HH__
+#define __ARCH_SPARC_ISA_HH__
+
+#include "arch/sparc/miscregfile.hh"
+#include "arch/sparc/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace SparcISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+
+        int instAsid()
+        {
+            return miscRegFile.getInstAsid();
+        }
+
+        int dataAsid()
+        {
+            return miscRegFile.getDataAsid();
+        }
+
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int flattenIntIndex(int reg);
+
+        int
+        flattenFloatIndex(int reg)
+        {
+            return reg;
+        }
+
+        void serialize(EventManager *em, std::ostream &os);
+        void unserialize(EventManager *em, Checkpoint *cp,
+                const std::string &section);
+
+        ISA()
+        {
+            clear();
+        }
+    };
+}
+
+#endif
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index a88c6c931..1daa43818 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -72,28 +72,6 @@ void RegFile::clear()
 {
     floatRegFile.clear();
     intRegFile.clear();
-    miscRegFile.clear();
-}
-
-MiscReg RegFile::readMiscRegNoEffect(int miscReg)
-{
-    return miscRegFile.readRegNoEffect(miscReg);
-}
-
-MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
-{
-    return miscRegFile.readReg(miscReg, tc);
-}
-
-void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
-{
-    miscRegFile.setRegNoEffect(miscReg, val);
-}
-
-void RegFile::setMiscReg(int miscReg, const MiscReg &val,
-        ThreadContext * tc)
-{
-    miscRegFile.setReg(miscReg, val, tc);
 }
 
 FloatReg RegFile::readFloatReg(int floatReg, int width)
@@ -151,80 +129,11 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
     intRegFile.setReg(intReg, val);
 }
 
-int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
-{
-    int gl = tc->readMiscRegNoEffect(MISCREG_GL);
-    int cwp = tc->readMiscRegNoEffect(MISCREG_CWP);
-    //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
-    int newReg;
-    //The total number of global registers
-    int numGlobals = (MaxGL + 1) * 8;
-    if(reg < 8)
-    {
-        //Global register
-        //Put it in the appropriate set of globals
-        newReg = reg + gl * 8;
-    }
-    else if(reg < NumIntArchRegs)
-    {
-        //Regular windowed register
-        //Put it in the window pointed to by cwp
-        newReg = numGlobals +
-            ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
-    }
-    else if(reg < NumIntArchRegs + NumMicroIntRegs)
-    {
-        //Microcode register
-        //Displace from the end of the regular registers
-        newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
-    }
-    else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
-    {
-        reg -= (NumIntArchRegs + NumMicroIntRegs);
-        if(reg < 8)
-        {
-            //Global register from the next window
-            //Put it in the appropriate set of globals
-            newReg = reg + gl * 8;
-        }
-        else
-        {
-            //Windowed register from the previous window
-            //Put it in the window before the one pointed to by cwp
-            newReg = numGlobals +
-                ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
-        }
-    }
-    else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
-    {
-        reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
-        if(reg < 8)
-        {
-            //Global register from the previous window
-            //Put it in the appropriate set of globals
-            newReg = reg + gl * 8;
-        }
-        else
-        {
-            //Windowed register from the next window
-            //Put it in the window after the one pointed to by cwp
-            newReg = numGlobals +
-                ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
-        }
-    }
-    else
-        panic("Tried to flatten invalid register index %d!\n", reg);
-    DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg);
-    return newReg;
-    //return intRegFile.flattenIndex(reg);
-}
-
 void
 RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
     floatRegFile.serialize(os);
-    miscRegFile.serialize(em, os);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
@@ -235,7 +144,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
     floatRegFile.unserialize(cp, section);
-    miscRegFile.unserialize(em, cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 7da302eb7..2333d9da5 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -65,31 +65,11 @@ namespace SparcISA
       protected:
         IntRegFile intRegFile;          // integer register file
         FloatRegFile floatRegFile;      // floating point register file
-        MiscRegFile miscRegFile;        // control register file
 
       public:
 
         void clear();
 
-        MiscReg readMiscRegNoEffect(int miscReg);
-
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
-
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val);
-
-        void setMiscReg(int miscReg, const MiscReg &val,
-                ThreadContext * tc);
-
-        int instAsid()
-        {
-            return miscRegFile.getInstAsid();
-        }
-
-        int dataAsid()
-        {
-            return miscRegFile.getDataAsid();
-        }
-
         FloatReg readFloatReg(int floatReg, int width);
 
         FloatReg readFloatReg(int floatReg);
@@ -117,14 +97,6 @@ namespace SparcISA
       public:
     };
 
-    int flattenIntIndex(ThreadContext * tc, int reg);
-
-    static inline int
-    flattenFloatIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
     void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 4c0460e28..96967ea24 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -96,6 +96,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('insts/microregop.cc')
     Source('insts/static_inst.cc')
     Source('intregfile.cc')
+    Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
     Source('predecoder.cc')
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
new file mode 100644
index 000000000..4d8c8bb67
--- /dev/null
+++ b/src/arch/x86/isa.cc
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/isa.hh"
+#include "arch/x86/floatregs.hh"
+#include "cpu/thread_context.hh"
+
+namespace X86ISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+int
+ISA::flattenIntIndex(int reg)
+{
+    //If we need to fold over the index to match byte semantics, do that.
+    //Otherwise, just strip off any extra bits and pass it through.
+    if (reg & (1 << 6))
+        return (reg & (~(1 << 6) - 0x4));
+    else
+        return (reg & ~(1 << 6));
+}
+
+int
+ISA::flattenFloatIndex(int reg)
+{
+    if (reg >= NUM_FLOATREGS) {
+        int top = miscRegFile.readRegNoEffect(MISCREG_X87_TOP);
+        reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
+    }
+    return reg;
+}
+
+void
+ISA::serialize(EventManager *em, std::ostream &os)
+{
+    miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
+{
+    miscRegFile.unserialize(cp, section);
+}
+
+}
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
new file mode 100644
index 000000000..34c803f0c
--- /dev/null
+++ b/src/arch/x86/isa.hh
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_ISA_HH__
+#define __ARCH_X86_ISA_HH__
+
+#include "arch/x86/miscregfile.hh"
+#include "arch/x86/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace X86ISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+        int instAsid()
+        {
+            //XXX This doesn't make sense in x86
+            return 0;
+        }
+
+        int dataAsid()
+        {
+            //XXX This doesn't make sense in x86
+            return 0;
+        }
+
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int flattenIntIndex(int reg);
+        int flattenFloatIndex(int reg);
+
+        void serialize(EventManager *em, std::ostream &os);
+        void unserialize(EventManager *em, Checkpoint *cp,
+                const std::string &section);
+    };
+}
+
+#endif
diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh
index 74dcbcbea..f2329b7b4 100644
--- a/src/arch/x86/miscregfile.hh
+++ b/src/arch/x86/miscregfile.hh
@@ -99,14 +99,10 @@ class Checkpoint;
 
 namespace X86ISA
 {
-    //These will have to be updated in the future.
-    const int NumMiscArchRegs = NUM_MISCREGS;
-    const int NumMiscRegs = NUM_MISCREGS;
-
     class MiscRegFile
     {
       protected:
-        MiscReg regVal[NumMiscRegs];
+        MiscReg regVal[NUM_MISCREGS];
         void updateHandyM5Reg(Efer efer, CR0 cr0,
                 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
 
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index c643a7924..54c7c9121 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -87,6 +87,7 @@
  */
 
 #include "arch/x86/isa_traits.hh"
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/process.hh"
 #include "arch/x86/segmentregs.hh"
 #include "arch/x86/types.hh"
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 83279902e..f6a9c1480 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -86,6 +86,7 @@
  */
 
 #include "arch/x86/floatregs.hh"
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/regfile.hh"
 #include "base/trace.hh"
 #include "sim/serialize.hh"
@@ -130,28 +131,6 @@ void RegFile::clear()
 {
     floatRegFile.clear();
     intRegFile.clear();
-    miscRegFile.clear();
-}
-
-MiscReg RegFile::readMiscRegNoEffect(int miscReg)
-{
-    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
-}
-
-MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
-{
-    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
-}
-
-void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
-{
-    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
-}
-
-void RegFile::setMiscReg(int miscReg, const MiscReg &val,
-        ThreadContext * tc)
-{
-    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
 }
 
 FloatReg RegFile::readFloatReg(int floatReg, int width)
@@ -209,50 +188,11 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
     intRegFile.setReg(intReg, val);
 }
 
-int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
-{
-    //If we need to fold over the index to match byte semantics, do that.
-    //Otherwise, just strip off any extra bits and pass it through.
-    if (reg & (1 << 6))
-        return (reg & (~(1 << 6) - 0x4));
-    else
-        return (reg & ~(1 << 6));
-}
-
-int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg)
-{
-    if (reg >= NUM_FLOATREGS) {
-        int top = tc->readMiscRegNoEffect(MISCREG_X87_TOP);
-        reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
-    }
-    return reg;
-}
-
-void
-RegFile::serialize(EventManager *em, std::ostream &os)
-{
-    intRegFile.serialize(os);
-    floatRegFile.serialize(os);
-    miscRegFile.serialize(os);
-    SERIALIZE_SCALAR(rip);
-    SERIALIZE_SCALAR(nextRip);
-}
-
 void
-RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
-{
-    intRegFile.unserialize(cp, section);
-    floatRegFile.unserialize(cp, section);
-    miscRegFile.unserialize(cp, section);
-    UNSERIALIZE_SCALAR(rip);
-    UNSERIALIZE_SCALAR(nextRip);
-}
-
-void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
-    //panic("copyMiscRegs not implemented for x86!\n");
     warn("copyMiscRegs is naively implemented for x86\n");
-    for (int i = 0; i < X86ISA::NumMiscRegs; ++i) {
+    for (int i = 0; i < NUM_MISCREGS; ++i) {
         if ( ( i != MISCREG_CR1 &&
              !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
              !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
@@ -260,10 +200,10 @@ void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
         }
         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
     }
-
 }
 
-void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
+void
+X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 {
     panic("copyRegs not implemented for x86!\n");
     //copy int regs
@@ -273,3 +213,17 @@ void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
     dest->setPC(src->readPC());
     dest->setNextPC(src->readNextPC());
 }
+
+void
+RegFile::serialize(EventManager *em, std::ostream &os)
+{
+    intRegFile.serialize(os);
+    floatRegFile.serialize(os);
+}
+
+void
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
+{
+    intRegFile.unserialize(cp, section);
+    floatRegFile.unserialize(cp, section);
+}
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index 4f285254a..0414622a2 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -62,8 +62,8 @@
 
 #include "arch/x86/floatregfile.hh"
 #include "arch/x86/intregfile.hh"
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/isa_traits.hh"
-#include "arch/x86/miscregfile.hh"
 #include "arch/x86/types.hh"
 #include "base/types.hh"
 
@@ -72,6 +72,9 @@ class EventManager;
 
 namespace X86ISA
 {
+    const int NumMiscArchRegs = NUM_MISCREGS;
+    const int NumMiscRegs = NUM_MISCREGS;
+
     class RegFile
     {
       protected:
@@ -91,33 +94,11 @@ namespace X86ISA
       protected:
         IntRegFile intRegFile; // integer register file
         FloatRegFile floatRegFile; // floating point register file
-        MiscRegFile miscRegFile; // control register file
 
       public:
 
         void clear();
 
-        MiscReg readMiscRegNoEffect(int miscReg);
-
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
-
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val);
-
-        void setMiscReg(int miscReg, const MiscReg &val,
-                ThreadContext * tc);
-
-        int instAsid()
-        {
-            //XXX This doesn't make sense in x86
-            return 0;
-        }
-
-        int dataAsid()
-        {
-            //XXX This doesn't make sense in x86
-            return 0;
-        }
-
         FloatReg readFloatReg(int floatReg, int width);
 
         FloatReg readFloatReg(int floatReg);
@@ -141,14 +122,8 @@ namespace X86ISA
         void serialize(EventManager *em, std::ostream &os);
         void unserialize(EventManager *em, Checkpoint *cp,
             const std::string &section);
-
-      public:
     };
 
-    int flattenIntIndex(ThreadContext * tc, int reg);
-
-    int flattenFloatIndex(ThreadContext * tc, int reg);
-
     void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 1478c3e66..c67c193ea 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -60,6 +60,7 @@
 #include "config/full_system.hh"
 
 #include "arch/x86/insts/microldstop.hh"
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/pagetable.hh"
 #include "arch/x86/tlb.hh"
 #include "arch/x86/x86_traits.hh"
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 9290dc024..dbb2bc361 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -58,6 +58,7 @@
 #ifndef __ARCH_X86_UTILITY_HH__
 #define __ARCH_X86_UTILITY_HH__
 
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/types.hh"
 #include "base/hashmap.hh"
 #include "base/misc.hh"