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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-18 13:19:49 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-10 10:15:05 +0000 |
| commit | 3a5ff476ffdcfcef2a6d0427d9add590984596e7 (patch) | |
| tree | 6e3992c2a60ddeea4322b1f9ac04800de37de5e7 /src/arch | |
| parent | 55a10a13f93ed5bbc12790bfcbdfbbf1975f0211 (diff) | |
| download | gem5-3a5ff476ffdcfcef2a6d0427d9add590984596e7.tar.xz | |
arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
gem5-ARM is not using floatRegs anymore and moved towards the
vecRegs register file (which is used for SIMD&FP + SVE instructions)
Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/insts/macromem.cc | 8 | ||||
| -rw-r--r-- | src/arch/arm/kvm/armv8_cpu.cc | 2 | ||||
| -rw-r--r-- | src/arch/arm/registers.hh | 1 |
3 files changed, 5 insertions, 6 deletions
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index eef2dfe27..7ed62f283 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -1123,7 +1123,7 @@ VldMultOp64::VldMultOp64(const char *mnem, ExtMachInst machInst, uint8_t numStructElems, uint8_t numRegs, bool wb) : PredMacroOp(mnem, machInst, __opClass) { - RegIndex vx = NumFloatV8ArchRegs / 4; + RegIndex vx = NumVecV8ArchRegs; RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn); bool baseIsSP = isSP((IntRegIndex) rnsp); @@ -1208,7 +1208,7 @@ VstMultOp64::VstMultOp64(const char *mnem, ExtMachInst machInst, uint8_t numStructElems, uint8_t numRegs, bool wb) : PredMacroOp(mnem, machInst, __opClass) { - RegIndex vx = NumFloatV8ArchRegs / 4; + RegIndex vx = NumVecV8ArchRegs; RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn); bool baseIsSP = isSP((IntRegIndex) rnsp); @@ -1297,7 +1297,7 @@ VldSingleOp64::VldSingleOp64(const char *mnem, ExtMachInst machInst, wb(false), replicate(false) { - RegIndex vx = NumFloatV8ArchRegs / 4; + RegIndex vx = NumVecV8ArchRegs; RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn); bool baseIsSP = isSP((IntRegIndex) rnsp); @@ -1370,7 +1370,7 @@ VstSingleOp64::VstSingleOp64(const char *mnem, ExtMachInst machInst, eSize(0), dataSize(0), numStructElems(0), index(0), wb(false), replicate(false) { - RegIndex vx = NumFloatV8ArchRegs / 4; + RegIndex vx = NumVecV8ArchRegs; RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn); bool baseIsSP = isSP((IntRegIndex) rnsp); diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc index 2ac97441d..cff138ce4 100644 --- a/src/arch/arm/kvm/armv8_cpu.cc +++ b/src/arch/arm/kvm/armv8_cpu.cc @@ -51,7 +51,7 @@ static_assert(NUM_XREGS == 31, "Unexpected number of aarch64 int. regs."); // The KVM interface accesses vector registers of 4 single precision // floats instead of individual registers. -constexpr static unsigned NUM_QREGS = NumFloatV8ArchRegs / 4; +constexpr static unsigned NUM_QREGS = NumVecV8ArchRegs; static_assert(NUM_QREGS == 32, "Unexpected number of aarch64 vector regs."); #define EXTRACT_FIELD(v, name) \ diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index 84f382b9c..1c9ec262a 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -82,7 +82,6 @@ using VecPredRegContainer = VecPredReg::Container; const int NumIntArchRegs = NUM_ARCH_INTREGS; // The number of single precision floating point registers const int NumFloatV7ArchRegs = 64; -const int NumFloatV8ArchRegs = 128; const int NumVecV7ArchRegs = 64; const int NumVecV8ArchRegs = 32; const int NumVecSpecialRegs = 8; |