Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5

into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge between ali and me.

--HG--
extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267

5 files changed, 51 insertions, 14 deletions

diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc
index 0a8ac055f..60856d3fa 100644
--- a/src/arch/sparc/intregfile.cc
+++ b/src/arch/sparc/intregfile.cc
@@ -111,6 +111,8 @@ void IntRegFile::setReg(int intReg, const IntReg &val)
 void IntRegFile::setCWP(int cwp)
 {
     int index = ((NWindows - cwp) % NWindows) * 2;
+    if (index < 0)
+        panic("Index less than 0. cwp=%d nwin=%d\n", cwp, NWindows);
     offset[Outputs] = FrameOffset + (index * RegsPerFrame);
     offset[Locals] = FrameOffset + ((index+1) * RegsPerFrame);
     offset[Inputs] = FrameOffset +
@@ -128,6 +130,11 @@ void IntRegFile::setGlobals(int gl)
 
     regView[Globals] = regGlobals[gl];
     offset[Globals] = RegGlobalOffset + gl * RegsPerFrame;
+
+    if (regView[Globals] == regView[Inputs] ||
+        regView[Globals] == regView[Locals] ||
+        regView[Globals] == regView[Outputs] )
+        panic("Two register arrays set to the same thing!\n");
 }
 
 void IntRegFile::serialize(std::ostream &os)
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index e2bebd987..2e1344a8f 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -184,7 +184,7 @@ decode OP default Unknown::unknown()
             }});
             0x0B: smul({{
                 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
-                Y = Rd.sdw;
+                Y = Rd.sdw<63:32>;
             }});
             0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
             0x0D: udivx({{
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index c58a1fd09..50f510289 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -326,12 +326,8 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
         return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
                mbits(tick,63,63);
       case MISCREG_FPRS:
-        warn("FPRS register read and FPU stuff not really implemented\n");
         // in legion if fp is enabled du and dl are set
-        if (fprs & 0x4)
-            return 0x7;
-        else
-            return 0;
+        return fprs | 0x3;
       case MISCREG_PCR:
       case MISCREG_PIC:
         panic("Performance Instrumentation not impl\n");
@@ -389,7 +385,6 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
         asi = val;
         break;
       case MISCREG_FPRS:
-        warn("FPU not really implemented writing %#X to FPRS\n", val);
         fprs = val;
         break;
       case MISCREG_TICK:
@@ -612,6 +607,8 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 void MiscRegFile::setRegWithEffect(int miscReg,
         const MiscReg &val, ThreadContext * tc)
 {
+    MiscReg new_val = val;
+
     switch (miscReg) {
       case MISCREG_STICK:
       case MISCREG_TICK:
@@ -634,7 +631,8 @@ void MiscRegFile::setRegWithEffect(int miscReg,
         tl = val;
         return;
       case MISCREG_CWP:
-        tc->changeRegFileContext(CONTEXT_CWP, val);
+        new_val = val > NWindows ? NWindows - 1 : val;
+        tc->changeRegFileContext(CONTEXT_CWP, new_val);
         break;
       case MISCREG_GL:
         tc->changeRegFileContext(CONTEXT_GLOBALS, val);
@@ -671,7 +669,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
       panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
 #endif
     }
-    setReg(miscReg, val);
+    setReg(miscReg, new_val);
 }
 
 void MiscRegFile::serialize(std::ostream & os)
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 40542a9a6..1cecb4ebb 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -625,13 +625,13 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
             return new DataAccessException;
         }
 
-    } else if (hpriv) {
+    } /*else if (hpriv) {*/
         if (asi == ASI_P) {
             ct = Primary;
             context = pri_context;
             goto continueDtbFlow;
         }
-    }
+    //}
 
     if (!implicit) {
         if (AsiIsLittle(asi))
@@ -933,6 +933,36 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
         pkt->set(data);
         break;
+      case ASI_IMMU_TSB_PS0_PTR_REG:
+        temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
+        if (bits(temp,12,0) == 0) {
+            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
+            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
+        } else {
+            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
+            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
+        }
+        data = mbits(tsbtemp,63,13);
+        data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
+            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
+        pkt->set(data);
+        break;
+      case ASI_IMMU_TSB_PS1_PTR_REG:
+        temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
+        if (bits(temp,12,0) == 0) {
+            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
+            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
+        } else {
+            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
+            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
+        }
+        data = mbits(tsbtemp,63,13);
+        if (bits(tsbtemp,12,12))
+            data |= ULL(1) << (13+bits(tsbtemp,3,0));
+        data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
+            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
+        pkt->set(data);
+        break;
 
       default:
 doMmuReadError:
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 128402fdd..b8a891c6d 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -44,8 +44,10 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
       case MISCREG_SOFTINT:
         // Check if we are going to interrupt because of something
         setReg(miscReg, val);
-        tc->getCpuPtr()->post_interrupt(soft_interrupt);
-        warn("Writing to softint not really supported, writing: %#x\n", val);
+        tc->getCpuPtr()->checkInterrupts = true;
+        tc->getCpuPtr()->post_interrupt(hstick_match);
+        if (val != 0x10000 && val != 0)
+            warn("Writing to softint not really supported, writing: %#x\n", val);
         break;
 
       case MISCREG_SOFTINT_CLR: