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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-29 14:44:45 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-29 14:44:45 -0500 |
| commit | 7545b2b65021b92044113f90fea26178cee7a44d (patch) | |
| tree | 82431b9ca5c749600b33b1157723dbfb51aae324 /src/arch | |
| parent | 852f26484f21e4ab9ed5bb889bae8388f59d8e67 (diff) | |
| parent | b37b6e17085c60c5db7256b84d97fd4184445ea7 (diff) | |
| download | gem5-7545b2b65021b92044113f90fea26178cee7a44d.tar.xz | |
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : 7b8b791815d1fb51cc7ad085307a640b2ee51642
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/sparc/floatregfile.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc index 1bb78c67b..6f04ca829 100644 --- a/src/arch/sparc/floatregfile.cc +++ b/src/arch/sparc/floatregfile.cc @@ -137,10 +137,12 @@ Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width) case SingleWidth: result32 = gtoh((uint32_t)val); memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); + DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32); break; case DoubleWidth: result64 = gtoh((uint64_t)val); memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); + DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64); break; case QuadWidth: panic("Quad width FP not implemented."); @@ -163,10 +165,12 @@ Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width) case SingleWidth: result32 = gtoh((uint32_t)val); memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); + DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result32); break; case DoubleWidth: result64 = gtoh((uint64_t)val); memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); + DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result64); break; case QuadWidth: panic("Quad width FP not implemented."); |