Merge Gabe and my changes to arch/mips/utility.hh

--HG--
extra : convert_revision : d5a9d74ee6edf71524ba5c03fb7f054cf9722213

15 files changed, 26 insertions, 130 deletions

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index af1a91a62..2177e8c4f 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -714,7 +714,7 @@ decode OPCODE default Unknown::unknown() {
             }}, IsNonSpeculative);
             0x83: callsys({{
                 xc->syscall(R0);
-            }}, IsSerializeAfter, IsNonSpeculative);
+            }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
             // Read uniq reg into ABI return value register (r0)
             0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
             // Write uniq reg with value from ABI arg register (r16)
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index de209348a..658710389 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -34,8 +34,9 @@ Import('*')
 
 if env['TARGET_ISA'] == 'mips':
     Source('faults.cc')
-    Source('isa_traits.cc')
+    Source('regfile/int_regfile.cc')
     Source('regfile/misc_regfile.cc')
+    Source('regfile/regfile.cc')
     Source('utility.cc')
     Source('dsp.cc')
 
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index e55d2e070..40ea223f6 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -134,7 +134,8 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
                     0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
                     0x4: syscall({{ xc->syscall(R2); }},
-                                 IsSerializeAfter, IsNonSpeculative);
+                                 IsSerializeAfter, IsNonSpeculative,
+                                 IsSyscall);
                     0x7: sync({{ ; }}, IsMemBarrier);
                 }
 
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 0e0cf44eb..0ce807a24 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -72,6 +72,7 @@ output exec {{
 #include "arch/mips/dsp.hh"
 #include "arch/mips/pra_constants.hh"
 #include "arch/mips/dt_constants.hh"
+#include "arch/mips/mt.hh"
 #include "arch/mips/mt_constants.hh"
 
 #include <math.h>
diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc
deleted file mode 100644
index 0c84ce2b2..000000000
--- a/src/arch/mips/isa_traits.cc
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Korey Sewell
- */
-
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/regfile/regfile.hh"
-#include "sim/serialize.hh"
-#include "base/bitfield.hh"
-
-using namespace MipsISA;
-using namespace std;
-
-void
-MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
-MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
-void
-MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
-{
-    panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
-void
-IntRegFile::serialize(std::ostream &os)
-{
-    SERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void
-IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void
-RegFile::serialize(std::ostream &os)
-{
-    intRegFile.serialize(os);
-    //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
-    //SERIALZE_ARRAY(miscRegFile);
-    //SERIALIZE_SCALAR(miscRegs.fpcr);
-    //SERIALIZE_SCALAR(miscRegs.lock_flag);
-    //SERIALIZE_SCALAR(miscRegs.lock_addr);
-    SERIALIZE_SCALAR(pc);
-    SERIALIZE_SCALAR(npc);
-    SERIALIZE_SCALAR(nnpc);
-}
-
-
-void
-RegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    intRegFile.unserialize(cp, section);
-    //UNSERIALIZE_ARRAY(floatRegFile);
-    //UNSERIALZE_ARRAY(miscRegFile);
-    //UNSERIALIZE_SCALAR(miscRegs.fpcr);
-    //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
-    //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
-    UNSERIALIZE_SCALAR(pc);
-    UNSERIALIZE_SCALAR(npc);
-    UNSERIALIZE_SCALAR(nnpc);
-
-}
-
-
diff --git a/src/arch/mips/mt_constants.hh b/src/arch/mips/mt_constants.hh
index 0f6978433..57306d237 100755
--- a/src/arch/mips/mt_constants.hh
+++ b/src/arch/mips/mt_constants.hh
@@ -31,7 +31,6 @@
 #ifndef __ARCH_MIPS_MT_CONSTANTS_HH__
 #define __ARCH_MIPS_MT_CONSTANTS_HH__
 
-#include "arch/mips/types.hh"
 //#include "config/full_system.hh"
 
 namespace MipsISA
diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index c97d93cf9..8f8899e92 100755
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -30,13 +30,13 @@
 
 #include "base/bitfield.hh"
 
-#include "arch/mips/regfile/misc_regfile.hh"
-#include "arch/mips/mt_constants.hh"
 #include "arch/mips/faults.hh"
+#include "arch/mips/mt.hh"
+#include "arch/mips/mt_constants.hh"
+#include "arch/mips/regfile/misc_regfile.hh"
 
-#include "cpu/thread_context.hh"
 #include "cpu/base.hh"
-#include "cpu/exetrace.hh"
+#include "cpu/thread_context.hh"
 //#include "cpu/mixie/cpu.hh"
 
 using namespace std;
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 54b086a8b..0846378bb 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -33,14 +33,12 @@
 
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/types.hh"
-#include "arch/mips/mt.hh"
-#include "arch/mips/mt_constants.hh"
-#include "base/bitfield.hh"
-#include "cpu/base.hh"
+#include "sim/eventq.hh"
 #include "sim/faults.hh"
 #include <queue>
 
 class ThreadContext;
+class BaseCPU;
 
 namespace MipsISA
 {
@@ -76,7 +74,10 @@ namespace MipsISA
 
         void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
 
-        void copyMiscRegs(ThreadContext *tc);
+        void copyMiscRegs(ThreadContext *tc)
+        {
+            panic("Copy Misc. Regs Not Implemented Yet\n");
+        }
 
         inline unsigned getVPENum(unsigned tid);
 
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index f13653132..b83bb576b 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -32,8 +32,6 @@
 #define __ARCH_MIPS_REGFILE_REGFILE_HH__
 
 #include "arch/mips/types.hh"
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/mt.hh"
 #include "arch/mips/regfile/int_regfile.hh"
 #include "arch/mips/regfile/float_regfile.hh"
 #include "arch/mips/regfile/misc_regfile.hh"
@@ -189,9 +187,11 @@ namespace MipsISA
         return reg;
     }
 
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
+    void
+    copyRegs(ThreadContext *src, ThreadContext *dest);
 
-    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+    void
+    copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
 } // namespace MipsISA
 
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 6195c4ceb..300761c93 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -74,8 +74,6 @@ namespace MipsISA {
 
     void startupCPU(ThreadContext *tc, int cpuId);
 
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
-
     // Instruction address compression hooks
     static inline Addr realPCToFetchPC(const Addr &addr) {
         return addr;
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 68b2183ad..14c652606 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1230,7 +1230,7 @@ decode OP default Unknown::unknown()
                         DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
                         fault = new TrapInstruction(lTrapNum);
                     }
-                }}, IsSerializeAfter, IsNonSpeculative);
+                }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
                 0x2: Trap::tccx({{
                     if(passesCondition(Ccr<7:4>, COND2))
                     {
@@ -1238,7 +1238,7 @@ decode OP default Unknown::unknown()
                         DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
                         fault = new TrapInstruction(lTrapNum);
                     }
-                }}, IsSerializeAfter, IsNonSpeculative);
+                }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
             }
             0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
                           MemWriteOp);
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index a8c4e7062..e8307c6e6 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -70,7 +70,7 @@
 #if FULL_SYSTEM
                 0x05: syscall();
 #else
-                0x05: SyscallInst::syscall('xc->syscall(rax)');
+                0x05: SyscallInst::syscall('xc->syscall(rax)', IsSyscall);
 #endif
                 0x06: clts();
                 //sandpile.org says (AMD) after sysret, so I might want to check
diff --git a/src/arch/x86/isa/decoder/x87.isa b/src/arch/x86/isa/decoder/x87.isa
index f16647fe5..bab687acd 100644
--- a/src/arch/x86/isa/decoder/x87.isa
+++ b/src/arch/x86/isa/decoder/x87.isa
@@ -103,7 +103,7 @@
                 0x5: fldln2();
                 0x6: fldz();
             }
-            default: fldcw();
+            default: fldcw_Mw();
         }
         0x6: decode MODRM_MOD {
             0x3: decode MODRM_RM {
@@ -129,7 +129,7 @@
                 0x6: fsin();
                 0x7: fcos();
             }
-            default: fnstcw();
+            default: fnstcw_Mw();
         }
     }
     //0x2: esc2();
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 18cbc6082..b8cddb09b 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -170,7 +170,7 @@ def template MicroLoadCompleteAcc {{
         %(op_rd)s;
 
         Mem = pkt->get<typeof(Mem)>();
-        int offset = pkt->flags;
+        int offset = pkt->req->getFlags();
         Mem = bits(Mem, (offset + dataSize) * 8 - 1,  offset * 8);
         %(code)s;
 
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 036805612..17904cb33 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -412,11 +412,6 @@ X86LiveProcess::argsInit(int intSize, int pageSize)
 
     initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
 
-    //Set up the thread context to start running the process
-    //Because of the peculiarities of how syscall works, I believe
-    //a process starts with r11 containing the value of eflags or maybe r11
-    //from before the call to execve. Empirically this value is 0x200.
-    threadContexts[0]->setIntReg(INTREG_R11, 0x200);
     //Set the stack pointer register
     threadContexts[0]->setIntReg(StackPointerReg, stack_min);