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authorGabe Black <gblack@eecs.umich.edu>2009-11-08 00:07:49 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-11-08 00:07:49 -0800
commita2b76516c453a946ab6220ad410be6d9e9c2777a (patch)
treefd113634ab6f86938b2bb066d2cd01818bb1de58 /src/arch
parent4a454c4f47362bd6f842fe1919f959a672ab1bb4 (diff)
downloadgem5-a2b76516c453a946ab6220ad410be6d9e9c2777a.tar.xz
ARM: Implement the shadow registers using register flattening.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa.hh43
1 files changed, 41 insertions, 2 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 9b21c03cd..1ad5428e5 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -44,14 +44,44 @@ namespace ArmISA
{
protected:
MiscReg miscRegs[NumMiscRegs];
+ const IntRegIndex *intRegMap;
+
+ void
+ updateRegMap(CPSR cpsr)
+ {
+ switch (cpsr.mode) {
+ case MODE_USER:
+ case MODE_SYSTEM:
+ intRegMap = IntRegUsrMap;
+ break;
+ case MODE_FIQ:
+ intRegMap = IntRegFiqMap;
+ break;
+ case MODE_IRQ:
+ intRegMap = IntRegIrqMap;
+ break;
+ case MODE_SVC:
+ intRegMap = IntRegSvcMap;
+ break;
+ case MODE_ABORT:
+ intRegMap = IntRegAbtMap;
+ break;
+ case MODE_UNDEFINED:
+ intRegMap = IntRegUndMap;
+ break;
+ default:
+ panic("Unrecognized mode setting in CPSR.\n");
+ }
+ }
public:
void clear()
{
memset(miscRegs, 0, sizeof(miscRegs));
CPSR cpsr = 0;
- cpsr.mode = MODE_USER;
+ cpsr.mode = MODE_SYSTEM;
miscRegs[MISCREG_CPSR] = cpsr;
+ updateRegMap(cpsr);
//XXX We need to initialize the rest of the state.
}
@@ -79,6 +109,9 @@ namespace ArmISA
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
{
+ if (misc_reg == MISCREG_CPSR) {
+ updateRegMap(val);
+ }
assert(misc_reg < NumMiscRegs);
miscRegs[misc_reg] = val;
}
@@ -86,7 +119,13 @@ namespace ArmISA
int
flattenIntIndex(int reg)
{
- return reg;
+ assert(reg >= 0);
+ if (reg < NUM_ARCH_INTREGS) {
+ return intRegMap[reg];
+ } else {
+ assert(reg < NUM_INTREGS);
+ return reg;
+ }
}
int